Samsung DVD-812 Service Manual page 64

5-6 DVD Data Processor
5-6-1 Outline
DIC1(KS1453) performs Sync detection, EFM demodulation and error correction and Spindle motor control (CLV
control) after inputting sliced EFM signal of RF signal at disc playback and EFM read clock (PLCK) signal generat-
ed from PLL. Outputs data which converted to the last audio and video from A/V decoder (ZIC1). KS1453 uses
external memory(4M DRAM) as buffer as well as for error correction and carries out Variable Bit Rate transfer func-
tion. VBR function uses the external buffer as buffer to absorb the difference of transfer rate occurring because the
transfer rate of disc playback is faster than data transfer rate demanded by A/V decoder(Video/Audio Signal
Process Chip).
In case of general disc refresh, the memory is almost filled up periodically. It is because Write rate to memory after
disc playback and signal process is faster than Read of A/V decoder. When the memory is filled, this status is report-
ed by interrupt to main micom, which controls the servo to kick back the pick-up to the previous track after mem-
orizing the last data read from disc until now. It takes some times to jump to the previous track and return to the
original(jump location) again. The memory will have an empty space because A/V decoder reads out data of mem-
ory.
When the memory has an empty space, where data can be processed and written and the pick-up correctly gets to
the original location(before kick back location) again, it reads data again avoids the interrupt of data read previ-
ously. The basic operation repeats to perform as described above.
5-6-2 Block Diagram
DIC2 (KM416C254)
D
1
5 .
.
0
D
D
1
5 .
.
0
EFM 116
EFMI
PLCK 104
PLCK
(KS1453)
MDP
109
MDS
110
Samsung Electronics
A
8 .
R C
.
A A W O
0
S S E E
D Z Z Z Z 14
A R C W O
D A A E E
95
R S S O O
8 .
.
0
SDATA[7..0]
69
CSTROBE
70
DATREQ
DIC1
58
DATACK
71
DTER
MDAT[7:0]
MRZA(3)
ZCS(2)
MWR(128)
MRD(127)
ZIRQZD(126)
1WAIT
MAD[7..0] INT7(ZIRQZD)
HA[10..8] INT8(/DVDINT)
*RD(88)
*WR(89)
HA0
MIC1 TMP95C265F
Fig. 5-29
Circuit Descriptions
CLOCK 27MHz
CLOCK 33.8688MHz
CLOCK 27MHz
159
DVD-D[7..0] zIC1
173
VSTROBE
(ZiVA4.1)
172
REQUEST
171
HDATA[7..0]
DACK
HADDR[2..0]
174
*ERR
/CS
/RD
/WR
/INT
ZWAIT
5-19