TYAN TOMCAT I915 User Manual page 34

Tomcat i915 S5120
CPU L1 & L2 Cache
This option toggles the use of CPU L1 and L2 cache. The L1 cache is also called the primary
cache or internal cache and is built into the processor. The L2 cache also called as the
external cache is placed between the CPU and the DRAM (dynamic RAM). A memory cache,
sometimes called a cache store or RAM cache, is a portion of memory made of high speed
static RAM (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main
memory. These caches store frequently accessed instructions and data. Memory caching is
effective because most programs access the same data or instructions over and over. By
keeping as much of this information as possible in SRAM, the computer avoids accessing the
slower DRAM.
•
Enabled
•
Disabled
Hyper-Threading Technology
This option allows you to enable or disable Hyper-Threading Technology. Hyper-Threading
Technology is a form of simultaneous multi-threading technology (SMT) where multiple
threads of software applications can be run simultaneously on one processor. This is achieved
by duplicating the architectural state on each processor, while sharing one set of processor
execution resources. Hyper-Threading Technology also delivers faster response times for
multi-tasking workload environments. By allowing the processor to use on-die resources that
would otherwise have been idle, Hyper- Threading Technology provides a performance boost
on multi-threading and multi-tasking operations.
•
Enabled
•
Disabled
APIC Mode
This option allows you to enable or disable Advanced Programmable
Interrupt Controller (APIC) Mode. APIC mode provides multi-processor interrupt management
and incorporates both static and dynamic symmetric interrupt distribution across all processors.
In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts.
Each interrupt pin is individually programmable as either edge or level triggered. The interrupt
vector and interrupt steering information can be specified per interrupt. An indirect register
accessing scheme optimizes the memory space needed to access the I/O APIC's internal
registers. To increase system flexibility when assigning memory space usage, the I/O APIC's
two-register memory space is re-locatable.
•
Enabled
•
Disabled
MPS Version Control For OS
This feature is only applicable to multiprocessor motherboards as it specifies the version of the
Multi-Processor Specification (MPS) that the motherboard will use. The MPS is a specification
by which PC manufacturers design and build Intel architecture systems with two or more
processors.
MPS 1.1 was the original specification. MPS version 1.4 adds extended configuration tables
for improved support of multiple PCI bus configurations and greater expandability in the future.
In addition, MPS 1.4 introduces support for a secondary PCI bus without requiring a PCI
bridge.
Once the operating system is installed, such as Windows XP, this setting
cannot be changed without reinstalling the operating system, regardless
of whether the initial setting is Disabled or Enabled.
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Note
3-7
Chapter 3: BIOS Setup