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Chapter 4
Chipset Features Setup
ROM PCI/ISA BIOS (2A59IT5A)
Auto Configuration
DRAM Timing
DRAM Leadoff Timing
DRAM Read Burst (EDO/FP)
DRAM Write Burst Timing
Fast EDO Lead Off
Refresh RAS# Assertion
Fast RAS To CAS delay
DRAM Page Idle Timer
DRAM Enhanced Paging
Fast MA to RAS# delay
SDRAM(CAS Lat/RAS-to-CAS) : 3/3
SDRAM Speculative Read
System BIOS Cacheable
Video BIOS Cacheable
8 Bit I/O Recovery Time
16 Bit I/O Recover Time
Memory Hole at 15M-16M
PCI 2.1 Compliance
Auto Configuration
This function selects the optimal values for your chipset parameters. If
Disabled, the chipset parameters will revert to setup information stored
in CMOS. When Auto Configuration is Enabled, many of the options
below will not be available.
DRAM Timing
The value in this field is determined by the performance parameters of
the installed DRAM chips. Unless you install new memory that has a
different performance rating than the factory DRAMs, you should not
alter this field.
DRAM Leadoff Timing
Selects the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Beware:
changing the value from the setting determined by the board designer
for the installed DRAM may cause memory errors.
CHIPSET SETUP UTILITY
AWARD SOFTWARE, INC.
: Enabled
Pipeline Cache Timing
: 70ns
Chipset NA# Asserted
Mem. Drive Str. (MA/RAS)
: 10/6/4
DRAM Refresh Rate
: x333/x444
CPU Warning Temperature
: x333
Current CPU Temperature
: Disabled
: 5 Clks
: 3
: 2 Clks
: Enabled
: 2 Clks
ESC : Quit
F1 : Help
: Disabled
F5 : Old Values
: Disabled
F6 : Load BIOS Defaults
: Disabled
F7 : Load Setup Defaults
: NA
: NA
: Disabled
: Disabled
36
: Faster
: Enabled
: Auto
: 15.6 us
: Disabled
: 3 5
C/ 95 F
éêè ç : Select Item
PU/PD/+/-
: Modify
(Shift)F2
: Color
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