Table Of Contents - Intel E6300 - Core 2 Duo Dual-Core Processor Datasheet

Contents
1
Introduction .............................................................................................................. 9
1.1 Terminology ....................................................................................................... 9
1.1.1 Processor Terminology Definitions ............................................................ 10
1.2 References ....................................................................................................... 11
2 Electrical Specifications ........................................................................................... 13
2.1 Power and Ground Lands.................................................................................... 13
2.2 Decoupling Guidelines ........................................................................................ 13
2.2.1 V
CC
2.2.2 V
TT
2.2.3 FSB Decoupling...................................................................................... 14
2.3 Voltage Identification ......................................................................................... 14
2.4 Reserved, Unused, and TESTHI Signals ................................................................ 16
2.5 Power Segment Identifier (PSID) ......................................................................... 16
2.6 Voltage and Current Specification ........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification ........................................................ 18
2.6.3 V
CC
2.6.4 Die Voltage Validation ............................................................................. 21
2.7 Signaling Specifications...................................................................................... 21
2.7.1 FSB Signal Groups.................................................................................. 22
2.7.2 CMOS and Open Drain Signals ................................................................. 23
2.7.3 Processor DC Specifications ..................................................................... 24
2.7.3.1
2.7.3.2
2.8 Clock Specifications ........................................................................................... 27
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 27
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 28
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 29
2.8.4 BCLK[1:0] Specifications ......................................................................... 29
3 Package Mechanical Specifications .......................................................................... 33
3.1 Package Mechanical Drawing............................................................................... 33
3.2 Processor Component Keep-Out Zones ................................................................. 37
3.3 Package Loading Specifications ........................................................................... 37
3.4 Package Handling Guidelines............................................................................... 37
3.5 Package Insertion Specifications.......................................................................... 38
3.6 Processor Mass Specification ............................................................................... 38
3.7 Processor Materials............................................................................................ 38
3.8 Processor Markings............................................................................................ 38
3.9 Processor Land Coordinates ................................................................................ 40
4 Land Listing and Signal Descriptions ....................................................................... 41
4.1 Processor Land Assignments ............................................................................... 41
4.2 Alphabetical Signals Reference ............................................................................ 64
5 Thermal Specifications and Design Considerations .................................................. 75
5.1 Processor Thermal Specifications ......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 78
5.2 Processor Thermal Features ................................................................................ 78
5.2.1 Thermal Monitor..................................................................................... 78
5.2.2 Thermal Monitor 2 .................................................................................. 79
5.2.3 On-Demand Mode .................................................................................. 80
5.2.4 PROCHOT# Signal .................................................................................. 81
5.2.5 THERMTRIP# Signal ............................................................................... 81
5.3 Platform Environment Control Interface (PECI) ...................................................... 82
Datasheet
Decoupling ...................................................................................... 13
Decoupling ...................................................................................... 13
Overshoot ....................................................................................... 20
Platform Environment Control Interface (PECI) DC Specifications..... 25
GTL+ Front Side Bus Specifications ............................................. 26
3