Kenwood DP-3010 Service Manual page 35

DP-3010
CIRCUIT DESCRIPTION
2) Focus/Tracking Servo System
Focus/Tracking Servo and Tracking Search system opera-
tions are actually divided into modes, as shown in Chart
7-4. Operations are done with a 2 MHz System Lock with
four clocks per mode.
SEL PIN
OuTPUT
MONITOR SIGNAL
>
UD1 ub2
SYSTEM MODE DIVISION
OPERATION DETAILS
+ +
Focus Gain Adjustmert
Focus Search
}
FE SBAD
Focus Gain Adjustment
Focus Search, FOK (Focus ON} Detection
Tracking Gain
TE RFRP
Adjustment
Tracking Gain Adjustment
RFRP Slice Level Caiculations Output
Non-Play
BAD
Normal Play af :
Scratch and Shock Detection
FOK 'Focus ON) Detection
4.
Special Play TE
Note #1:
Note #2:
Note #3:
64
Tracking Search TE
Shock Detection
RF Zero Cross Detection
Tracking Search
Chart 7-4 Focus/Tracking Servo Mode Division
TC9201BF deterr.nes the information input
from TA8101N witn the SEL Output Signal
The four signals, F= (Focus Error), TE (Tracking
Error), SBAD (Sut-veam Summing) and RFRP
(RF Ripple} are divided into three by the SEL
Output Signal.
Non-Play is the cendition in which eventhough
the DMSV Command (CLV Servo ON) is set.
Tracking is OFF (Detailed explanation excluded)
Special Play is tne condition after Tracking
Search is complete and the next mode. Detailed
explanation is done in the Tracking Search
System.
The Focus/Tracking System is operated in accordance to
the CPU Process Flow Chart on Page 79.
Starting with the Focus Gain System, the operation expla-
nations of the systems in order are in the following.
DP-3010
CIRCUIT DESCRIPTION
(1) Focus Gain Adjustment (FGA) System
TA8101N
{ }
9
(a)
a
TC9201 BF
Diagram 7-20 System Construction Diagram
Correlation Pins: FKIC, FEL1, FEL2, SEL
Commands: FGASS(88xx), FGASR(89xx)
FGASET(8Axx)
Write Command ({CM-A)
Command Reception
Conditions: LDON(84xx)
Command Set
Mode Selector SEL
l Vv I
REF Hiz
I Vv I
REF Hiz
Peak Date Set
|
FELI
Focus Gain
Adjustment Pin
FEL2
Peak Hold
2CLi
(FE)
Command fl l ll ll
FE Signat
c n va a
wn
@ < g a
io} Qo QO ¢
re w iL oO
ost Ww
TEGA
TFGA: Time interval is determined by the CPU
Diagram 7-21 Timing Chart (1)
65