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Panasonic SA-AK100P User Manual page 40

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Pin No.
Mark
58
X1 IN
I
59
X2 OUT
O
60
VDD
I
61
BYTCK
-
62
/CLDCK -
63
FCLK
-
64
IPFLAG
-
65
FLAG
-
66
CLVS
-
67
CRC
-
68
DEMPH
-
69
RESY
-
70
IOSEL
I
71
/TEST
I
72
AVDD1
I
73
OUTL
O
74
AVSS1
I
75
OUTR
O
I/O
Function
Crystal oscillating
circuit input (f =
16.9344MHz)
Crystal oscillating
circuit input (f =
16.9344 MHz)
Power supply input
(for oscillating circuit)
Byte clock output
Sub-code frame clock
signal output
(fCLDCK = 7.35 kHz
during normal
playback)
Crystal frame clock
signal output (fCLK =
7.35 kHz, double =
14.7 kHz)
Interpolation flag
output ("H" :
Interpolation)
Flag output
Spindle servo phase
synchronizing signal
output ("H" : CLV,
"L" : rough servo)
Sub-code CRC
checked output ("H' :
OK, "L" :NG)
De-emphassis ON
signal output ("H" :
ON)
Frame re-
synchronizing signal
output
Mode Switching
Terminal
Test input
Power supply input
(for analog circuit)
Left channel audio
signal output
GND
Right channel audio
signal output
40

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