Status Register C; Status Register D - IBM Personal System/2 50 Technical Reference

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Status Register C (Hex OOC)
Bit
Function
7
Interrupt Request Flag
6
Periodic Interrupt Flag
5
Alarm Interrupt Flag
4
Update-Ended Interrupt Flag
3 - 0
Reserved
Figure
3-14. Status Register C
Note: Interrupts are enabled by bits 6, 5, and 4 in Status Register B.
Bit 7
This bit is used in conjunction with bits 6, 5,and 4. When
set to 1, this bit indicates that an interrupt has occurred;
bits 6,5, and 4 indicate the type of interrupt.
Bit 6
When set to 1, this bit indicates that a periodic interrupt
occurred.
Bit 5
When set to 1, this bit indicates that an alarm interrupt
occurred.
Bit 4
When set to 1, this bit indicates that an update-ended
interrupt occurred.
Bits 3 - 0
Reserved.
Status Register D (Hex OOD)
Bit
Function
7
Valid RAM
6 - 0
Reserved
Figure
3-15. Status Register 0
Bit 7
This read-only bit monitors the power-sense pin. A low
state of this pin indicates a loss of power to the real-time
clock (dead battery). When set to 1, this bit indicates that
the real-time clock has power. When set to 0, it indicates
that the real-time clock has lost power.
Bits 6 - 0
Reserved.
3-18
Model 50 System Board

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