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3. Common
PLL
The VCO output from Q1: 2SK125 is buffered by Q2
and Q3: 2SC2668(Y), is switched by diode D2:
1S2588,
and is then sent to the RX unit as the RXO signal (receiver
1st local osc.). A sample of this signal is coupled to pre-
scaler U21:
uwPC571C
from
the output
of Q2
through
buffer Q5: 2SC2668(Y).
The prescaler acts as a 1/64 or 1/65 divider con-
trolled
by the
pulse
generated
by PLL
IC U18
pin 9
(MC145152) and its output is further divided by the ~ N-
counter U18: then it is coupled to the phase comparator.
The output of the reference oscillator Z1:
TCXO
is
divided by U18
after buffering by Q6 and is coupled to the
phase comparator.
The dividing ratio is determined
by
16-bit
parallel
data
set
by PROM
ICs U22
and
U23:
M54730AP.
The dividing ratio of the reference oscillator
output is locked.
The output of the phase comparator is
fed through the charge pump U20:
TC4007UBP
and the
loop filter and is then coupled back to varicap diode D1:
1 SV50E as the VCO control voltage.
RXO frequency range: fi (MHz)
F1
F2
F3
F4
f. formula:
fL (MHz)
128.6000 ~ 138.6000
134.6000 ~ 141.6000
140.6000 ~ 147.6000
146.6000 ~ 152.6000
If the TX frequency is fT'
fp=fr-21.4
N value range (f;: PLL TXO output):
N=25720 ~ 30520
formula:
N=8- 214 1000
TXO(+lOdBm) RXO(+8dBm)
Fig. 4-8 PLL Block Diagram
4-5
Address
bus for I6CH/32CH
TK-701
SKHz
comparison
0. 24 MHz
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