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CIRCUIT DESCRIPTION
re)
Description
D/A interface,
bit clock
Bit clock input(48bit slot ) for DAC
GTOP output
XUGF output
XPLCK output
GFS output
RFCK output
GND
C2PO output
XRAOF output
MNT3 output
MNT1 output
MNTO output
Output 2/3 divided f of 33,8688MHz
4.2336MHz output
Digital output
CD Emphasis
H: EX1ST
L: Non
DAC demphasis ON/OFF, H : ON, L : OFF
WRITE FRAME CLOCK output
No sound data detected output, H : No sound(Lch)
No sound data detected output,
H : No sound(Rch)
DAC test terminal 1, normal L
DAC Digital power supply
Lch PWM output(Reverse phase)
Lch PWM output(Normal phase)
PWM driver power supply
Xtal power supply
33.8688MHz Xtal OSC input
33.8688MHz Xtal OSC output
Xtal GND
PWM driver GND
Rch PWM output(Reverse phase)
iF Rech PWM output(Normal phase)
DAC test terminal 2, normal L
DAC test terminal 3, normal L
0/0;
0;/0/0;-|
0
4
—|
0/0;
0};—-|/
0);
0;0;/0;0/0;0;0;0
NOTES:
-"PCMD" is 2-S complementary output of "MSB First."
- "GTOP' is used to monitor the protective conditions of FrameSync (where "H" indicates "Sync protective window open").
-"XUGEF" is a FrameSync obtained from the EFM signal, which is a negative pulse. This is a signal before Sync protection.
- "XPLICK" means to reverse the EFM PLL clock. The PLL is designed to match the falling edge with the changing point sf the
EFM signal.
-"GFS signal" is a signal that causes "H" when the FrameSync is matched with interpolation protective timing.
-"RFCK" is a 136- usec. cycle signal that can be obtained at Xtal accuracy.
-"C2PO" is a signal that indicates the error status of the data.
~ "XRAOF' is a signal that occurs when the 16K RAM exceeds the jitter margin of +4F.
30
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