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General Description
Power-up NMI.
Upon power-up, self-test is always run first. After successful completion of self-
test, the power-up load jumper is examined. If the jumper is not installed, the loader is executed. If
the jumper is installed, the host/auxiliary jumper is examined. If the CPU is a host and has battery
backup, a level 0 interrupt trap (power restored) is taken. If the CPU
is a host but has no battery
backup, a load is performed unless a front panel is present. If a front panel is present, front panel
code is executed.
If the CPU is an auxiliary, map 0 is set up to map logical address 0 to the on-board memory lower-
bound address and mapping is enabled. The CPU then idles after executing a LIMI 3 to enable the
multiprocessor interrupt.
Nonpower-up NMI.
An NMI occurring from some condition other than power-up always results in
front panel code execution if a front panel is present. If no front panel is present, then a load is per-
formed if the CPU is a host, or a LIMI 3, IDLE if the CPU is an auxiliary. The front panel code operates
the same for both hosts and auxiliaries.
1.5.6
Communication Register Unit (CRU) Controller
The 990/10A
is compatible
with all standard
CRU
interfaces,
but allows
32,768
output
bits and
32,768 input bits, instead of the 4096 allowed by previous processors.
In addition, multiple bit
transfers are made in parallel mode on the 990/10A board. This provides high-speed transfers to the
address mapping chip and diagnostic hardware. Parallel transfers off the processor board are not
supported. Only the 12 low order CRU bits are available off the 990/10A board, and CRU addresses
for off-board functions are compatible with all existing 990 family hardware and software.
NOTE
The 990/10A uses the three MSBs of the CRU address field for inter-
nal addressing and any attempt to issue a CRU access to an address
with any of the three MSBs of register 12 set to a logic one may cause
erroneous results.
Both input and output bits can be addressed
individually or in fields of from 1 to 16 bits. The pro-
cessor employs three dedicated I/O pins (CRUBITIN, CRUBITOUT,
and STORECLK-)
and 12 bits
(CRUBIT4 through CRUBIT15) of the address bus at the interface to the CRU system. The processor
instructions that drive the CRU interface can set, reset, or test any bit in the CRU array or move data
between memory and CRU data fields.
The processor performs three single-bit CRU functions: test bit (TB), set bit to one (SBO), and set bit
to zero (SBZ). To identify the bit to be operated on, the processor develops a CRU-bit address and
places it on the address bus, CRUBIT4 through CRUBIT15.
2302633-9701
1-17
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