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logic, and 65,536 bytes of memory. The 65,536 bytes
are organized into 32,768 22-bit words. Sixteen-bit
words are read from or written to memory over the
TILINE; byte selection is performed in the 990
CPU. The 6-bit Hamming code is internal to the
ECC memory boards.
The ECC controller board can control an add-on
expansion board in the adjacent slot via a top-edge
interconnection. Switches on the controller board set
the starting memory address anywhere in the
TILINE address space on 16K -byte boundaries.
Correctable and noncorrectable error indicators on
each ECC controller board give a visual indication
for servicing ease. Noncorrectable (2-bit) errors also
send an interrupt to the 990 CPU.
The 128K-byte memory, which is standard for
DS990 systems, consists of one 64K-byte ECC
controller board and one 64K-byte ECC expansion
board. Additional space is available within the
chassis for future memory expansion. The amount of
semiconductor memory needed in a system is
determined by many factors. These factors include
the number of simultaneously operated interactive
terminals, the size and organization_of the
application programs, and the high-level languages
selected. Refer to Appendixes C and D for
additional information on memory-size selection.
990 TILINE
The TILINE is a multiuser, asynchronous, parallel
data bus. This bus, which is capable of more than
three million 16-bit word transfers per second, links
the 990 CPU, memories, and high-speed peripheral
controllers.
Bus communications are based on a master-slave
relationship between TILINE devices. Slave devices,
such as 990 memory, respond to a 20-bit word
address and control signals by supplying or accepting
a 16-bit word. Each word transfer is accompanied by
an exchange of "handshaking" control signals.
Master devices, such as the 990 CPU, compete for
access to the bus. A reservation scheme allows bus-
access operations to partially overlap, reducing the
overhead time to transfer control between masters.
Conflicts between masters attempting to reserve the
bus are resolved by a positional priority scheme
based. on chassis-slot location.
The high-speed "smart" peripheral controllers for
the DS 10, DS31, DS25, or DS50 hard disks and the
979A magnetic-tape system are TILINE devices that
act as masters and as slaves at different times. They
act as slaves when they accept a set of eight to
sixteen setup and command parameters from the 990
CPU, and they act as masters when they perform
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the specified-record read or \yrite operation between
990 memory and disk or tape drive.
Some applications of the 990 processor require
more circuit boards than can physically fit in the
standard thirteen-slot chassis. Both of the 990 1/0
systems (the CRU and the TILINE) can be extended
into additional chassis modules using the appropriate
kit.
Communications Register Unit
The communications register unit (CRU) is the
general-purpose 110 system for the 990 processor.
This versatile, command-driven, synchronous 1/0
system has proved to be the most flexible system yet
developed for low- and intermediate-speed
applications. The CRU provides communications
between the CPU and device controller for VDTs,
data terminals, card readers, printers, the
programmer panel, and other low- and medium-
speed devices.
The CR U has two 4096-bit registers: one for input
and one for output. Each bit is individually
addressable. Direct addressing of CPU input and
output bits is the key to the versatility of the CRU
system. A single 990 instruction can read from (or
write to) an individual bit or a group of up to 16
bits.
The 990 CPU performs partial decoding of the 12-
bit CR U address to produce a group of module-
select signals, which are hard-wired to the available
half-slot locations in the chassis. This simplifies
address decoding on the individual full-sized logic
boards and imposes a positional addressing scheme.
The CR U interface can be extended to additional
chassis if system requirements exceed the available
space for logic boards.
TILINE Peripherals
The TILINE peripherals are high-speed I/O systems
which transfer data to and from 990 memory at
rates that approach the instruction execution rate of
the 990 computer. These systems include the DS31,
DSIO, DS25, and DS50 hard-disk systems and the
979A magnetic-tape system. All are used for
nonvolatile mass-memory storage to supplement the
semiconductor memory in the 990 computer.
Each of the TILINE peripherals consists of one or
more electromechanical recording/ reproducing devices
(disk drive or tape transport), a recording medium
(disk pack, disk cartridge, or magnetic tape), and a
microprocessor-based "smart" controller, which
occupies a full slot in the 990 chassis.
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