Fet Driver Turn-Off - Texas Instruments 2 Series Manual

BQ76905
SLUSE97 – NOVEMBER 2023
Figure 8-5 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP
for a 5-series pack, with [FET_EN] = 1 for autonomous FET control and providing the [INITCOMP] flag on the
ALERT pin. The TS pin is pulled up to initiate device wakeup from SHUTDOWN. The TS pin voltage is shown in
blue; the DSG pin voltage is shown in green.

8.2.6 FET Driver Turn-Off

The low-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective
FET. The DSG driver includes an internal switch that drives the DSG pin toward the VSS pin level when the
driver is disabled. The driver is specified with a maximum fall time into a 20-nF capacitive load, with 100-Ω series
resistance between the DSG pin and the DSG gate. If the driver is used with a larger capacitive load, the fall
time generally increases. The system designer can optimize the series resistance value based on the board
components and DSG FET(s) used.
The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the
turn-off transient. A low resistance (such as 100 Ω) provides a fast turn-off during a short circuit event, but this
can result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value
(such as 1 kΩ or 4.7 kΩ) reduces this speed and the corresponding inductive spike level.
The CHG FET driver discharges the CHG pin toward the VSS pin level, but it includes an additional series
PFET in order to support voltages below VSS. This is generally needed when a pack is heavily discharged, for
example, if cells in a 5S pack are at 2.5 V per cell, then PACK+ = 12.5 V relative to device VSS. Then if a
charger is attached while the CHG FET is disabled and applies a full charge voltage across PACK+ relative to
PACK-, such as 4.3 V per cell, or 21.5 V for the 5S pack, this results in PACK– dropping to approximately –9 V
relative to VSS. In order to keep the CHG FET disabled, its gate voltage must drop to near this –9 V level.
To support this type of case, the CHG FET driver in BQ76905 is designed to withstand voltages as low as –25 V
(recommended) relative to the VSS pin voltage by including a series PFET at the pin, with its gate connected to
VSS. When the CHG driver is disabled, the driver pulls the pin voltage downward. As the pin voltage nears VSS,
the PFET is disabled, so the pin becomes high impedance. At this point, the external gate-source resistor on the
CHG FET pulls the pin voltage lower to the PACK– level, keeping the CHG FET disabled.
Oscilloscope captures of CHG and DSG driver turn-off are shown below, with the pins driving the gates of
CSD18532Q5B NFETs, which have a typical C
48 Submit Document Feedback
Figure 8-5. Startup Sequence for a 5-Series Pack
of 3900 pF.
iss
Product Folder Links:
Figure 8-6 shows the signals when using a 1.35-kΩ
Copyright © 2023 Texas Instruments Incorporated
BQ76905
www.ti.com