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IC BLOCK DIAGRAM AND DESCRIPTION
IC42S16800-7T(2Mx8 bitsx4 banks Synchronous Dynamic RAM)
PIN FUNCTIONS
Symbol
CLK
CKE
CS
RAS, CAS, WE
A0-A11
BA0,BA1
DQM, UDQM ,LDQM
DQ0 to DQ15
V
V
Power Supply Pin
DD
,
SS
V
V
Power Supply Pin
,
DDQ
SSQ
Type
Function (In Detail)
Input Pin
Master Clock: Other inputs signals are referenced to the CLK rising edge
Input Pin
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals,device input buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).
Input Pin
Chip Select: CS enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. CS is considered part of the command code.
Input Pin
Command Inputs:
being entered.
Input Pin
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and AUTO PRECHARGE bit for READ/WRITE
commands, to select one location out of the memory array in the respective
bank. The row address is specified by A0-A11. The column address is
specified by A0-A8 (IC42S16800)
Input Pin
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Input Pin
Din Mask / Output Disable: When DQM is high in burst write, Din for the
current cycle is masked. When DQM is is high in burst read, Dout is
disable at the next but one cycle.
I/O Pin
Data Input / Output: Data bus.
Power Supply for the memory array and peripheral circuitry.
Power Supply are supplied to the output buffers only.
RAS , CAS and WE (along with CS) define the command
TX-NR1000
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