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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
BU1924FS (RDS Decoder) <European model only>
BLOCK DIAGRAM
100k
MUX
(4)
120k
100k
(3)
Vref
V
DD1
(5)
Analog
Power supply
(6)
V
SS1
(12)
V
DD2
Digital
Power supply
(11)
V
SS2
(13)
XI
anti-aliasing
filter
PLL
PLL
57kHz
1187.5Hz
RDS/ARI
Reference
clock
(14)
XO
TERMINAL DESCRIPTION
Pin No.
Pin name
Description
1
QUAL
Output terminal of demodulator quality signal.
2
RDATA
Output terminal of demodulator data.
3
Vref
Input terminal of reference voltage.
4
MUX
Input terminal of composite signal.
5
V
Analog power supply.
DD1
6
V
Analog power supply.
SS1
7
Ground.
V
SS3
8
CMP
Input terminal of comparator.
9
T2
Input terminal for test mode.
10
T1
Input terminal for test mode.
11
V
Digital power supply.
SS2
12
V
Digital power supply.
DD2
13
XI
Connect to oscillator.
14
XO
Connect to oscillator.
15
(N.C.)
---
16
RCLK
Output terminal of demodulator clock.
V
SS3
(7)
8th Switched
capacitor filter
comparator
Bi-phase
Differential
decoder
decoder
Measurement
circuit
(10)
(9)
T1
T2
TX-NR1000
CMP
(8)
RCLK
(16)
QUAL
(1)
RDATA
(2)
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