Denon DCD-3520 Service Manual page 30

30
SENS
DIRC
XRST
DATA
XLT
CLK
SSTOP
nN
Serial data input from CPU.
Latch input from CPU.
Serial data transfer clock input from CPU.
Terminal for external time constant of loop filter,
Input terminal of PDO for CXD1125 phase comparator.
VCOF
C864 Output terminal of 8.64 MHz VCO.
—
39 LOCK
Reckless drive protection circuit activates at "L".
A47kQ pull up resistor is included,
40 MOP
Terminal to connect MDP terminal of CXD1125.
ey oe
Tr
46 WDCK
Clock input for auto-sequence.
Normally applied 88.2 kHz.
47 FOK
FOK signal input terminal.
MIRR
MIRR signal input terminal.
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