Sanyo LCE-32R83DT Service Manual page 31

TAS5707, TAS5707A
PIN
NAME NO.
AGND 30
AVDD 13
AVSS 9
BST_A 4
BST_B 43
BST_C 42
BST_D 33
DVDD 27
DVSSO 17
DVSS 28
FAULT 14
GND 29
GVDD_OUT 5, 32
LRCLK 20
MCLK 15
NC 8
OC_ADJ 7
OSC_RES 16
OUT_A 1
OUT_B 46
OUT_C 39
OUT_D 36
PDN 19
PGND_AB 47, 48
PGND_CD 37, 38
PLL_FLTM 10
PLL_FLTP 11
PVDD_A 2, 3
PVDD_B 44, 45
PVDD_C 40, 41
PVDD_D 34, 35
RESET 25
SCL 24
SCLK 21
SDA 23
SDIN 22
TYPE 5-V TERMINATION
(1)
TOLERANT
P
P
P
P
P
P
P
P
P
P
DO
P
P
DI 5-V Pulldown
DI 5-V Pulldown
–
AO
AO
O
O
O
O
DI 5-V Pullup
P
P
AO
AO
P
P
P
P
DI 5-V Pullup
DI 5-V
DI 5-V Pulldown
DIO 5-V
DI 5-V Pulldown
PIN FUNCTIONS
(2)
Analog ground for power stage
3.3-V analog power supply
Analog 3.3-V supply ground
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
3.3-V digital power supply
Oscillator ground
Digital ground
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
Analog ground for power stage
Gate drive internal regulator output
Input serial audio data left/right clock (sample rate clock)
Master clock input
No connection
Analog overcurrent programming. Requires resistor to ground.
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating PWM stop
sequence.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
2
I C serial control clock input
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
2
I C serial control data interface input/output
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
DESCRIPTION