Sony UP-860 Service Manual page 44

5-3. GATE ARRAY 1IC102 PERIPHERAL CIRCUITS
Gate array 1C102 comprises the following blocks :
(1) Registers for storing serial data from the CPU (for mode setting)
(2) Frame memory write/read control
(3) 1-line print timing generation
(4) Thermal head control
(5) Dither signal generation
(6) Syne/signal processing
(7) 1-lime memory
The operation of each block is determined by the serial data from the CPU and
the mode switch terminals.
5-3-1. Operations
1.
When the CPU has judged the states for DIP switch (S302), it sends 64-bit
serial data to the shift register in gate array IC102. The data sets the modes for
all the blocks in the gate array.
2.
When the Fetch pulse from the CPU is input to IC102-€0, the data for the next
frame is written into the frame memory. The WEO signal at 1C102-@ changes this
way:
1C102-@ Fetch Sey kt ns ee ee
1C102-@
= EXTV
eee
Frame unit rr
cs@s Gobieven. a) — — oe
1C102-@ WEO | | | |
Writing Writing
3. {Print timing generation
INTV, the timing pulse for printing one line is made by counting down the FG
pulses for the DC servo motor. The count down number, N, is determined by the
serial data from the CPU. Changing this value changes the print period and, since
the motor speed is fixed, changes the print line pitch. In only the PAL 1:1 mode,
the INTV pulse is produced in realtime irrespective of the FG pulse. The time
constant at that time is determined by the serial data from the CPU. IC102
watches the FG pulse and stops the INTV pulse when the FG pulse stops for more
than a fitted time period. In addition to the print timing, the INTV pulse is used
to detect the CPU motor speed. The CPU judges the motor speed from the INTV
pulse period and stops the motor if it detects any abnormality.
is Count down number, N
fei C02 Se 5 CHEE he
a SE
1C102- wih oe
INTY sen
aS