Motorola M68MPB16Z3 User Manual page 33

Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
Pin
8
9
10
11
12
13
14
15
16
M68MPB16Z3UM/D
Mnemonic
LAT-DSI LATCHED INSTRUCTION PIPE 1 – Latched output
(Latched IPIPE1) signal of the first state of IPIPE1 for CPU16-based
MCUs; indicates instruction pipeline activity.
DSO / DEVELOPMENT SERIAL OUT – Serial data output
signal for background debug mode.
(IPIPE0) INSTRUCTION PIPE 0 for CPU16-based MCUs.
DSI / DEVELOPMENT SERIAL IN – Serial data input signal
for background debug mode.
(IPIPE1) INSTRUCTION PIPE 1 for CPU16-based MCUs.
DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
DSACK0 DATA AND SIZE ACKNOWLEDGE 0 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
FC2 / FUNCTION CODE 2 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS5 CHIP SELECT 5 – Output signal that selects peripheral
or memory devices at programmed addresses.
FC1 / FUNCTION CODE 1 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS4 CHIP SELECT 4 – Output signal that selects peripheral
or memory devices at programmed addresses.
FC0 / FUNCTION CODE 0 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS3 CHIP SELECT 3 – Output signal that selects peripheral
or memory devices at programmed addresses.
SIZ3 TRANSFER SIZE – Output signal that indicate the
number of bytes still to be transferred during this cycle.
MEVB SUPPORT INFORMATION
Signal
4-5