Ni 6581/6581B Component-Level Intellectual Property (Clip) - National Instruments NI 6581 Getting Started Manual

Digital I/O signals, P0 <0..7>, P1 <0..7>, P2 <0..7>, and PFI <1..3>, appear
Note
on both connectors, DDCA and DDCB.
Refer to Tables 3 and 4 for information about buffer mapping to the NI
Note
FlexRIO FPGA module.
NI 6581/6581B Component-Level Intellectual
Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. NI FlexRIO devices support two types of CLIP: user-defined and socketed.
• User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
Socketed CLIP provides the same IP integration of the user-defined CLIP, but also allows
•
the CLIP to communicate directly with circuitry external to the FPGA. Adapter module
socketed CLIP allows your IP to communicate directly with both the FPGA VI and the
external adapter module connector interface.
The following figure shows the relationship between an FPGA VI and the CLIP.
Figure 7. PFI <1..3> Port
PFI from
3
NI FlexRIO
FPGA Module
PFI Output Enable
from NI FlexRIO
FPGA Module
PFI to
NI FlexRIO
FPGA Module
Figure 8. Clock Input and Output
Global Clock
to NI FlexRIO
FPGA Module
Clock from
NI FlexRIO
FPGA Module
Output Enable
from NI FlexRIO
FPGA Module
NI 6581/6581B Getting Started Guide | © National Instruments | 11
Voltage Reference
Internal/External
3
Voltage Reference
Internal/External
DDC Global
Clock In
DDC
Clock Out
3
DDC