National Instruments PCIe-6323 User Manual page 187

Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the filter clock has sampled the signal high
on N consecutive edges, the low to high transition is propagated to the rest of the circuit. The
value of N depends on the filter setting; refer to Table 8-1.
Filter Setting
None
90 ns
(short)
5.12 µs
(medium)
2.56 ms
(high)
Custom
The filter setting for each input can be configured independently. On power up, the filters are
disabled. Figure 8-3 shows an example of a low to high transition on an input that has a custom
filter set to N = 5.
RTSI, PFI, or
PXI_STAR Terminal
Filter Clock
Filtered Input
Enabling filters introduces jitter on the input signal. The maximum jitter is one period of the
timebase.
When a RTSI input is routed directly to PFI, the X Series device does not use the filtered version
of the input signal.
Table 8-1. Filters
Filter Clock Pass Signal)
—
100 MHz
100 MHz
100 kHz
User
configurable
Figure 8-3. Filter Example
1 1 2 3
N (Filter
Clocks Pulse Width
Needed to Guaranteed
to Pass Filter
—
9
512
256
N N/timebase
4 1 2 3
X Series User Manual
Pulse Width
Guaranteed
to Not Pass
—
90 ns
5.12 µs
2.56 ms 2.55 ms
timebase
Filtered input goes
high when terminal
4 5
is sampled high on
five consecutive filter
clocks.
© National Instruments | 8-5
Filter
—
80 ns
5.11 µs
(N - 1)/