National Instruments PCIe-6323 User Manual page 131

The filter setting for each input can be configured independently. On power up, the filters are
disabled. Figure 6-12 shows an example of a low-to-high transition on an input.
Digital Input P0. x
Filter Clock
Filtered Input
When multiple lines are configured with the same filter settings they are considered a bus. There
are two filtering modes for use with multiple lines: line filtering and bus filtering. With line
filtering, each line transitions independently of the other lines in the bus and acts like the
behavior described above. With bus filtering, if any one line in the bus has jitter then all lines in
the bus hold the state until the bus becomes stable. However, each individual line only waits
one extra filter tick before changing, which prevents a noisy line from holding a valid transition
indefinitely. With bus mode if all the bus line transitions become stable in less than one filter
clock period and the bus period is more than two filter clock periods, then all the bus lines are
guaranteed to be correlated at the output of the filter.
The behavior for each transition can be thought of as a state machine. If a line transitions and
stays high for two consecutive filter clock edges, then one of two options occurs:
• Case 1—If no transitions have occurred on the other lines, the transition propagates on the
second filtered clock edge, as shown in Figure 6-13.
Figure 6-12. Input Low-to-High Transition
1
Figure 6-13. Case 1
Digital Input P0.A
Digital Input P0.B
Filter Clock
Filtered Input A
Filtered Input B
1 1 1
Stable Stable Stable
X Series User Manual
2 1 2
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