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DDR5 Only DIMM Configuration
SPR IMC#
H
Channel
Chan 7
DDR5
H0 H1 G0 G1 F0 F1 E0 E1
1+0
2+0
4+0
V
6+0
V
V
8+0
V
V
12+0
V
16+0
V
⚠
Note
1. There should be at least one DDR5 DIMM per socket.
2. Interleaving way limitations: 3-way Channel and 3-Way Rank interleaving are not
supported. A 2-Way + A 1-Way would be implemented instead of A 3-Way for those
channel DIMM configurations. A 2-way interleave method is implemented across 3
ranks in a channel.
3. Sapphire Rapids processor erratum prevents using 6-way Hemisphere mode,
6-way All-to-All mode would be the default for 6 channel configurations.
4. If the system detects a DIMM fails at boot time, BIOS takes map-out actions for a
fallback to the nearest reduced POR config in the table.
5. Rank sparing, ADDDC, channel mirroring, and Hemisphere/ quad modes are not
supported with SGX.
6. SPR+HBM does not support Hemisphere/ SNC2 modes.
7. UMA default - see 6-DIMM configurations, x6 interleaving for All-to-All mode.
IMC3
IMC2
G
F
Chan 6
Chan 5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
"V" indicates DIMMs are populated with DDR5.
IMC0
E
A
Chan 4
Chan 0
A1 A0 B1 B0 C1 C0 D1 D0
V
V
C
V
P
V
U
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IMC1
B
C
D
Chan 1
Chan 2
Chan 3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CPU & Heatsink
V
V
V
V
V
V
V
35
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