Sharp LC-32WD1RU Service Manual page 59

LC-32WD1E/S/RU and LC-32WT1E
D030 HDMI receiver
D041 EEPROM
D070 EEPROM
D071 EEPROM
D061 LVDS IC
D1301 Video Switch
D1302
D0705 EEPROM
D1410 Amtel processor
Analogue Part (Audio)
D020 Class D AMP
D022 Audio Switch
TDA9975AEL/10 The TDA9975A is a combination of a three inputs triple 10-bit
video converter interface and of a two inputs High-Definition
Multimedia Interface (HDMI) receiver with embedded HDCP
keys memory.
The IC converts a YUV (YPBPR) analogue signal into a YUV
(YCBCR) or RGB digital signal or converts an RGB analogue
signal into a RGB or YUV (YCBCR) digital signal with a
sampling rate up to 100 Mbps.
M24C32-WMN6 These I2C-compatible electrically erasable programmable
memory (EEPROM) devices are organized as 4096 × 8 bits.
M24C02-WMN6 These I2C-compatible electrically erasable programmable
memory (EEPROM) devices are organized as 128 x 8.
M24C02-WMN6 These I2C-compatible electrically erasable programmable
memory (EEPROM) devices are organized as 128 x 8.
DS90C385AMT The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are
sampled and transmitted. At a transmit clock frequency of 85
MHz, 24 bits of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of
595 Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 297.5 Mbytes/sec.
TDA8601T/C2 The device is intended for switching between two RGB or YUV
video sources. The outputs can be set to a high-impedance
state to enable parallel connection of several devices. A HIGH
level on SEL (pin 5) selects the video inputs of channel 2. The
IOCNTR control pin (pin 16) defines the 3-state outputs and
clamp inputs:
TDA8601T/C2
• HIGH = 3-state outputs (also for test; active clamp)
• LOW = passive clamp at the video inputs (diode)
• Sandcastle: the video signal is clamped with an active clamp
during the sync pulse.
M24C02-WMN6 These I2C-compatible electrically erasable programmable
memory (EEPROM) devices are organized as 128 x 8.
ATTINY2313V-10 The AVR core combines a rich instruction set with 32 general
purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more
code efficient while achieving throughputs up to ten times
faster than conventional CISC micro controllers.
TDA8932T This is a Switched Mode Amplifier (SMA) for audio, based on
the TDA8932 or TDA8933 device of Philips Semiconductors
operating from an asymmetrical supply.
The TDA8932 device and the TDA8933 device are pin-to-pin
compatible and can be used in either a stereo SE configuration
or a mono BTL configuration. The TDA8932 is the high-power
version and the TDA8933 is the low-power version and
together cover a wide power range per channel of 5 WRMS to
50 WRMS. The two versions are available in the SO32
package and HTSSOP32 package.
TEA6422D The TEA6422 switches 6 stereo audio inputs on 3 stereo
outputs.
All the switching possibilities are changed through the I2C
BUS.
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