Intel Agilex 7 FPGA I Series User Manual page 55

A. Development Kit Components
721605 | 2023.04.10
Schematic Signal Name
mux_sel13
mux_sel14
mux_sel_zl
mcio_clk_enn
mcio_clk_sel_epn
si5332_1_in[1:0]
si5332_1_in[2]
PTP_CLK_RST_n
PTP_CLK_LOL
gpio0_ac0_zl_intn
Table 12. UB2/PWR Intel MAX 10
Schematic Signal Name
FPGA_POK_LED
SYS_PWR_RSV0
SYS_PWR_RSV1
SYS_PWR_RSV2
SYS_PWR_RSV3
Send Feedback
system_info_slv_data_write_0[12]=0
MUX_DIP_SW6
system_info_slv_data_write_0[13]=1
system_info_slv_data_write_1[13]
system_info_slv_data_write_0[13]=0
MUX_DIP_SW8
system_info_slv_data_write_0[14]=1
system_info_slv_data_write_1[14]
system_info_slv_data_write_0[14]=0
MUX_DIP_SW7
system_info_slv_data_write_0[15]=1
system_info_slv_data_write_1[15]
system_info_slv_data_write_0[15]=0
SYS_SW4
Before power ok: 1
After power ok:
system_info_slv_data_write_0[16]=1
S_control_gui[8]
system_info_slv_data_write_0[16]=0
• =0 when AGIB027R31B is Endpoint
• =1 when AGIB027R31B is Root port
S_control_gui[5:4]
1'bZ
Before power ok: 0
After power ok:
Store in
status_gui bit1
Store in
status_gui bit0
FPGA Power Good
Reserved GPIO between System Intel MAX 10 and Power
Intel MAX 10. Used as I
Reserved GPIO between System Intel MAX 10 and Power
Intel MAX 10. Used as I
Reserved GPIO between System Intel MAX 10 and Power
Intel MAX 10. It is the status of
Reserved GPIO between System Intel MAX 10 and Power
Intel MAX 10
®
Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
Description
, =0 by default
S_control_gui[7]
, =0 by default
, =00 by default
, =1 by default
S_control_gui[6]
Description
2
C clock.
2
C data.
.
SYS_PB3
: controlled by
: controlled by
: controlled by
: controlled by
: controlled by
: controlled by
: controlled by
: controlled by
:
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