Intel Agilex 7 FPGA I Series User Manual page 54

Schematic Signal Name
mux_sel1
mux_sel2
mux_sel3
mux_sel4
mux_sel5
mux_sel6
mux_sel7
mux_sel8
mux_sel9
mux_sel10
mux_sel11
mux_sel12
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Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
54
A. Development Kit Components
Description
system_info_slv_data_write_0[0]=0
MUX_DIP_SW10
system_info_slv_data_write_0[1]=1
system_info_slv_data_write_1[1]
system_info_slv_data_write_0[1]=0
SYS_SW1
system_info_slv_data_write_0[2]=1
system_info_slv_data_write_1[2]
system_info_slv_data_write_0[2]=0
MUX_DIP_SW0
system_info_slv_data_write_0[3]=1
system_info_slv_data_write_1[3]
system_info_slv_data_write_0[3]=0
MUX_DIP_SW1
system_info_slv_data_write_0[4]=1
system_info_slv_data_write_1[4]
system_info_slv_data_write_0[4]=0
MUX_DIP_SW2
system_info_slv_data_write_0[5]=1
system_info_slv_data_write_1[5]
system_info_slv_data_write_0[5]=0
MUX_DIP_SW3
system_info_slv_data_write_0[6]=1
system_info_slv_data_write_1[6]
system_info_slv_data_write_0[6]=0
MUX_DIP_SW9
system_info_slv_data_write_0[7]=1
system_info_slv_data_write_1[7]
system_info_slv_data_write_0[7]=0
SYS_SW2
system_info_slv_data_write_0[8]=1
system_info_slv_data_write_1[8]
system_info_slv_data_write_0[8]=0
MUX_DIP_SW11
system_info_slv_data_write_0[9]=1
system_info_slv_data_write_1[9]
system_info_slv_data_write_0[9]=0
SYS_SW3
system_info_slv_data_write_0[10]=1
system_info_slv_data_write_1[10]
system_info_slv_data_write_0[10]=0
MUX_DIP_SW4
system_info_slv_data_write_0[11]=1
system_info_slv_data_write_1[11]
system_info_slv_data_write_0[11]=0
MUX_DIP_SW5
system_info_slv_data_write_0[12]=1
system_info_slv_data_write_1[12]
721605 | 2023.04.10
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