Intel Agilex 7 FPGA I Series User Manual page 46

Mode
001
100
Others
®
Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
46
S20 [4:2]
ON/ON/OFF
OFF/ON/ON
N/A
A. Development Kit Components
S19 [4] [3] [2] [1]
ON: Bypass from chain
OFF: Enable in chain
SDM is always enabled in
the JTAG chain.
S19.1 (HPS)
S19.2 (System Intel MAX
10)
S19.3 (FMC_B)
S19.4 (FMC_A)
S19.1 (SDM)
S19.2 (System Intel MAX
10)
S19.3 (FMC_B)
S19.4 (FMC_A)
N/A
721605 | 2023.04.10
Function
Mode 3: External Intel FPGA
Download Cable act as the
only JTAG Master. Chained
HPS with SDM nodes
internally.
Mode 2: On-board Intel
download circuit act as the
only JTAG Master. Chained
HPS with SDM nodes
externally.
Mode 4: External Intel FPGA
Download Cable act as the
only JTAG Master. Chained
HPS with SDM node
externally.
Mode 7: Both on-board Intel
download circuit and OOBE
act as JTAG Masters.
Separated HPS and SDM
JTAG chains, OOBE only
drive HPS.
Mode 8: Both external Intel
FPGA Download Cable and
OOBE JTAG act as JTAG
Masters.
Separated HPS and SDM
JTAG chains, OOBE only
drive HPS.
Reserved
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