Table Of Contents - Intel Agilex 7 FPGA I Series User Manual

Contents
1. Overview........................................................................................................................ 4
1.1. Block Diagram.......................................................................................................6
1.2. Feature Summary..................................................................................................6
1.3. Box Contents........................................................................................................ 7
1.4. Recommended Operating Conditions........................................................................ 7
2. Getting Started............................................................................................................... 8
2.1. Intel Quartus
2.2. Design Examples................................................................................................... 8
3. Power Up the Development Kit..................................................................................... 10
3.1. Default Settings...................................................................................................10
3.2. Power Up............................................................................................................ 11
3.3. Perform Board Restore..........................................................................................12
3.3.1. Restore Board System Intel MAX 10 with Default Factory Image.....................12
3.3.2. Restore Board QSPI Flash with Default Factory Image................................... 12
4. Board Test System........................................................................................................ 13
4.1. Set Up BTS GUI Running Environment.................................................................... 14
4.1.1. Download OpenJDK.................................................................................. 14
4.1.2. Download OpenJFX.................................................................................. 15
4.1.3. Install OpenJDK and OpenJFX.................................................................... 15
4.1.4. Install Intel Quartus Prime Software........................................................... 15
4.1.5. Run BTS GUI........................................................................................... 16
4.2. Test the Functionality of the Development Kit.......................................................... 17
4.2.1. The Bottom Info Bar.................................................................................17
4.2.2. The Configure Menu................................................................................. 17
4.2.3. The Sys Info Tab...................................................................................... 18
4.2.4. The GPIO Tab.......................................................................................... 19
4.2.5. The XCVR Tab..........................................................................................21
4.2.6. The Memory Tab...................................................................................... 30
4.3. Control On-Board Clock through Clock Controller GUI............................................... 33
4.4. Monitor On-Board Power Regulator through Power Monitor GUI.................................. 37
4.5. BTS Test Areas.................................................................................................... 38
4.6. Identify Test Pass or Fail-based on BTS GUI Test Status.............................................38
5. Development Kit Hardware and Configuration.............................................................. 39
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG...................................... 39
5.2. Configure the FPGA Device Using the AS Mode (Default Mode)................................... 39
5.3. Configure the FPGA Device Using the Avalon-ST Mode.............................................. 39
5.4. Daughter Cards................................................................................................... 40
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card....................................... 40
6. Custom Projects for the Development Kit..................................................................... 41
6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File....................................... 41
6.2. Golden Top......................................................................................................... 42
7. Document Revision History for the Intel Agilex 7 FPGA I-Series Transceiver-SoC
Development Kit User Guide.................................................................................... 43
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Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
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Prime Software and Driver Installation................................................ 8
Contents
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