Sharp XL-30V Service Manual page 60

XL-30V
IC15V VHiES3880F/-1: Video CD Decoder (ES3880F)
Pin No. Terminal Name
1 VDD
2 RAS#
3 DWE#
4-12 DA0-DA8
13-28 DBUS0-DBUS15
29 RESET#
30 VSS
31 VDD
32-39 YUV0-YUV7
40 VSYNC
41 HSYNC
42* CPUCLK
43 PCLK2X
44 PCLK
45-49 AUX0-AUX4
50 VSS
51 VDD
52-54 AUX5-AUX7
55-62 LD0-LD7
63* LWR#
64 LOE#
65 LCS3#
66,67* LCS1#, LCS0#
68-79 LA0-LA11
80 VSS
81 VPP
82-87 LA12-LA17
88 ACLK
89 AOUT/SEL_PLL0
90 ATCLK
91 ATFS/SEL_PLL1
92 DA9/DOE#
93 AIN
94 ARCLK
95 ARFS
96 TDMCLK
97 TDMDR
98 TDMFS
99 CAS#
100 VSS
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input Voltage supply for 3.3V.
Output DRAM row address strobe (active low).
Output DRAM write enable (active low).
Output DRAM multiplaxed row and column address bus.
Input/Output DRAM data bus.
Input Ayatem reset (active low).
Input Ground.
Input Voltage supply for 3.3V.
Output Y is luminance, UV are chrominance data bus for screen video interface.
YUV0-YUV7 for 8-bit YUV mode.
Input/Output Vertival sync for screen video interface, programmable for rising or falling edge.
Input/Output Horizontal sync for screen video interface, programmable for rising or falling edge.
Input RISC and system clock input. CPUCLK is used only if SEL_PLL0, SEL_PLL1=00.
Input/Output Pixel clock; two times the actual pixel clock for screen video interface.
Input/Output Pixel clock qualifier in for screen video interface.
Input/Output Auxiliary control pins (AUX0 and AUX1 are open collectors).
Input Ground.
Input Voltage supply for 3.3V.
Input/Output Auxiliary control pins.
Input/Output RISC interface data bus.
Output RISC interface write enable (active low).
Output RISC interface output enable (active low).
Output RISC interface chip enable (active low).
Output RISC interface chip enable (active low).
Output RISC interface address bus.
Input Ground.
Input Digital supply voltage for 5V.
Output RISC interface address bus.
Input/Output Master clock for external audio DAC (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344
MHz and 18.432 MHz).
Output Dual-purpose pin. AOUT is the audio interface serial data output.
Input Pins SEL_PLL0, SEL_PLL1 select phase-lock loop (PLL) clock frequency CPUCLK for the
Visba:
00 = bypass PLL.
01 = 54 MHz PLL.
10 = 67.5 MHz PLL.
11 = 81 MHz PLL.
Input/Output Audio transmit bit clock.
Output Dual-purpose pin. ATFS is the audio interface transmit frame sync.
Input Pins SEL_PLL0, SEL_PLL1 select phase-lock loop (PLL) clock frequency CPUCLK for tha
Viaba.
See the SEL_PLL0 pin above for the settings.
Output Dual purpose pin: DRAM output enable (active low)/DRAM multiplexed row column
address bus.
Input Audio interface serial data input.
Input Audio receive bit clock.
Input Audio interface receive frame sync.
Input TDM interface serial clock.
Input TDM interface serial data receive.
Input TDM interface frame sync.
Output DRAM column address strobe bank 0 (active low).
Input Ground.
Function
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