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IC14V VHiES3883F/-1: Video CD Encoder (ES3883F) (1/2)
Pin No.
Terminal Name
1
VSS
2*-4*
NC
5
VCC
6
DSC_C
7*
AUX0
8
DSC_D0
9*
AUX1
10
DSC_S
11*
AUX2
12*
DCLK/EXT_CLK
13
RESET_B
14*
AUX07
15*
MUTE
16
VCC
17
MCLK
18*
AUX8
19
TWS/SPLL_OUT
20*
AUX09
21
TSD
22
TBCK
23
RWS/SEL_PLL1
23
RWS/SEL_PLL1
24
RSTOUT_B
25, 26
VSS
27*
NC (SQCK)
28*
NC (SQSO)
29*, 30*
NC
31
VSS
32
VCC
33
RSD/SEL_PLL0
33
RSD/SEL_PLL0
34*
AUX10
35*
AUX11
36*
AUX12
37
RBCK/SER_IN
38
AUX13
39*
AUX14
40*
AUX15
41
VSSA
42
VCM
43
VREFP
44
VCCAA
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input
Ground.
—
No connect. Do not connect to these pins.
Input
Voltage supply, 5V.
Input
Clock for programming to access internal registers.
Input/Output
Servo Forward Control pin.
Input/Output
Data for programming to access internal registers.
Input/Output
Servo Reverse Control pin.
Input
Strobe for programming to access internal registers.
Input/Output
Servo LDON or Control pin.
Output
Dual-purpose pin. DCLK is the MPEG decoder clock.
Input
EXT_CLK is the extemal clock. EXT_CLK is an input during bypass PLL mode.
Input
Video reset (active low).
Input/Output
Servo BRKM/Sense or Control pin/VFD_DI.
Output
Audio mute.
Input
Voltage supply, 5V.
Input
Audio master clock.
Input/Output
Servo Mute/Open or Control pin/VFD_CLK.
Input
Dual-purpose pin. TWS is the transmit audio frame sync.
Output
SPLL_OUT is the select PLL output.
Input/Output
Servo SQS0 or Control pin.
Input
Transmit audio data input.
Input
Transmit audio bit clock.
Output
Dual-purpose pin. RWS is the receive audio frame sync.
Input
Pins SEL_PLL [1:0] select the PLL clock frequency for DCLK output.
SEL_PLL1
0
0
1
1
Output
Reset output (active low).
Input
Ground.
—
No connect. Do not connect to these pins.
—
No connect. Do not connect to these pins.
—
No connect. Do not connect to these pins.
Input
Ground.
Input
Voltage supply, 5V.
Output
Dual-purpose pin. RSD is the receive audio data input.
Input
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output.
See the table for pin number 23.
Input/Output
Servo SQCK or Control pin.
Input/Output
3880 IRQ or Interrupt Output or Control pin.
Input/Output
CD C2PO or Interrupt or Control pins.
Output
Dual purpose pin. RBCK is the receive audio bit clock.
Input
SER_IN is serial input DSC mode.
0 = Parallel DSC mode.
1 = Serial DSC mode.
Input/Output
Serial Interrupt/CD-Mute or Control pin.
Input/Output
Servo SCOR(S0S1) or Interrupt Input or Control pin.
Input/Output
Interrupt Input or Control pin.
Input
Audio Analog ground.
Input
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V.
Bypass to analog ground with 47 µF electrolytic in parallel with 0.1 µF.
DAC and ADC maximum reference. Bypass to VCMR with 10 µF in parallel with 0.1 µF.
Input
Input
Analog VCC, 5V.
Function
SEL_PLL0
DCLK
0
Bypass PLL (Input Mode)
1
27MHz (Output Mode)
0
32.4MHz (Output Mode)
1
40.5MHz (Output Mode)
– 57 –
XL-30V
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