Asus PRIME Intel 500 Series Manual page 17

DRAM Refresh Interval
Configuration options: [Auto] [1] – [65535]
DRAM WRITE Recovery Time
Configuration options: [Auto] [1] – [31]
DRAM READ to PRE Time
Configuration options: [Auto] [1] – [15]
DRAM FOUR ACT WIN Time
Configuration options: [Auto] [1] – [63]
DRAM WRITE to READ Delay / DRAM WRITE to READ Delay L /
DRAM WRITE to READ Delay S
Configuration options: [Auto] [1] – [15]
DRAM CKE Minimum Pulse Width
Configuration options: [Auto] [0] – [15]
DRAM Write Latency
Configuration options: [Auto] [1] – [31]
Skew Control
ODT RTT WR (CHA) / ODT RTT WR (CHB)
Configuration options: [Auto] [0 DRAM Clock] [80 DRAM Clock]
ODT RTT PARK (CHA) / ODT RTT NOM (CHA) / ODT RTT PARK (CHB) /
ODT RTT NOM (CHB)
Configuration options: [Auto] [0 DRAM Clock] [34 DRAM Clock]
ODT_READ_DURATION / ODT_READ_DELAY / ODT_WRITE_DURATION /
ODT_WRITE_DELAY
Configuration options: [Auto] [0] – [7]
Data Rising Slope / Cmd Rising Slope / Ctl Rising Slope / Clk Rising Slope /
Data Falling Slope / Cmd Falling Slope / Ctl Falling Slope / Clk Falling Slope
Configuration options: [Auto] [0] – [15]
Data Rising Slope Offset / Cmd Rising Slope Offset /
Ctl Rising Slope Offset / Clk Rising Slope Offset /
Data Falling Slope Offset / Cmd Falling Slope Offset /
Ctl Falling Slope Offset / Clk Falling Slope Offset
Configuration options: [Auto] [0] [1]
RTL IOL Control
DRAM RTL INIT value
Configuration options: [Auto] [0] – [127]
DRAM IOL INIT value(CHA) / DRAM IOL INIT value(CHB)
Configuration options: [Auto] [0] – [15]
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[120 DRAM Clock] [240 DRAM Clock] [255 DRAM Clock]
[40 DRAM Clock] [48 DRAM Clock] [60 DRAM Clock]
[80 DRAM Clock] [120 DRAM Clock] [240 DRAM Clock]
500 Series BIOS Manual
® 17