Motorola MTR2000 Manual page 108

VCC
U4006
9
I0
8
Reset*
OUT
10
I1
SPI_CLK_CNTL
SPI_CLK_DEL_CNTL
VCC
RESET CIRCUIT
VCC
Reset_Switch*
C4001
D4000
0.1uF
U4007 2
D4001
N5 15
6
VCC
MR
7
RESET
1
8
VBATT VOUT
5
4
PFI PFO
C4000
GND
100uF
3
1
Serial_ID_In*
XTAL
C4010
EXTAL
1.2MHz
XFC
MODCLK0
.01uF
VCCSYN
21 MODCLK1
R4052
1
VCC PB11
16
4.7K
PB10
Ref_Control_in(0:4) 11 11
PB9
PB8
1
R4021
PB2
See Note
VCC PB1
20
47K
PB0
BRG2 /PA7
Backplane_in(0:21)
47K
R4049
VCC BRG1
R4022
RCLK2
Mic_PTT*
0
VCC TCLK2
1
47K
Flash_Pwr_En* CD2*
2
CTS2*
3
RTS2*
4
RXD2
5
TXD2
SCC2(0:5)
RCLK1
TCLK1
VCC CD1*
CTS1*
2
RTS1*
0
RXD1
1
TXD1
SCC1(0:2)
N5 14
0
N5 2
1 VCC
N5 13
2
SPI(0:2)
SCC3(0:1)
1
SP_Control_out(0:11)
0
N5 5 N5 1
1
N5 4 N5 20
2
N5 6
3
N5 7
4
N5 9
5
N5 8
6
N5 11
7
N5 10
Host_Data(0:7)
R4051
10K VCC
1
3 4
U4006
2 6
U4006
5
9 N4
VCC
10 N4
11 N4
4 N4
3
N4
2 3 4
/PA3
0 1
2 1 0
BI-DIRECTIONAL
DATA BUS DRIVERS
0 1
3 2 4 7 6 5
3 0
16 N4
2 1
1 N6 14 N4
4 2
20
N6 15 N4
7 3
20 7
N4 N4
6 4
1 N4 8
N4
5 5
13 N4
6
7
B
VCC
C4002
0.1uF
Host_Address(0:19)
3 N5
0
12 N4
1
2 N6
2
3 N6
3
N6
5
0
4
A0/ UDS* N6
4
5
LDS* 6 N6
1 6
A1 7 N6
2 7
A2
10 N6
3 8
A3 9 N6
4 9
A4 8 N6
5
10
A5 13 N6
6 11
A6 11 N6
7 12
A7 14 N6
8 13
A8
12 N6
9 14
A9 N6
16
10
15
A10 15 N6
11 16
A11 17 N6
12 17
A12 18 N6
13 18
A13
19 N6
14 19
A14
15 0
A15 17 N5
16 1
A16 16 N5
17
2
A17 12 N5
18
A18 R4050
19
A19
0
A20 0
D4003
1
A21
2
A22
3
A23
4
FC0
5
FC1
D4002
C
6
FC2
NC1
NC2
RP_bus(0:6)
NC3
0 R4026
NC4
1 R4027
NC5
2 R4028
3 R4029
4 R4030
5 R4031
0 1 2 3 4 5 6 7
2 3 4 5 6 7
6 R4032
R_Data(0:7)
0 R4033
VCC
U4005
1 R4034
20
VCC 2 R4035
19 3 R4036
EN_OE
1 4 R4037
C4008
T_R*
5 R4038
6 R4039
18 2 0
0.1uF
Y0 D0
7 R4040
17 3 1
Y1 D1
16 4
2
Y2 D2
15 5
3
Y3 D3
14 6
4
Y4 D4
13 7
5
Y5 D5
12 8 6
Y6 D6
11 9 7
Y7 D7
GND
10
Host_Master_Data(0:7)
STATION CONTROL MODULE
Contr_P(0:5)
C4003
1uF
0 2
1
A
32
VCC
24
EN_OE
29
EN_WE
22
U4001
CS1
17 30 17
CS2
0 12 13 0 0
A0 D0
11 14
1 1 1
A1 D1
2 10 15 2
2
A2 D2
3 9 17 3
3
A3 D3
4 8 18 4
4
A4 D4
5 7 19 5 5
A5 D5
6 6 20 6 6
A6 D6
5 21
7 7 7
A7 D7
8 27 8
A8
9 26 9
A9
10 23 10
A10
11 25 11
A11
12 4 12
A12
13 28 13
A13
14 3 14
A14
15 31 15
A15
16 2 1 16
A16 NC
VSS
16
VCC
18
18
12V
C4006
1 23
0.1uF
VPP VCC
12
EN_CE
14
EN_OE
43
EN_WE
33
BYTE
44
RP
47K 6
EN_CS1
U4003
47K 1 11 15 4
0
A0 D0 EN_CS2
47K 2 10 17 5
1
A1 D1 EN_CS3
47K
3 9 19
2
A2 D2
47K
4 8 21 15 1
3
A3 D3 A0
47K 5 7 24 16 2
4
A4 D4 A1
47K 6 6 26 17 3
5
A5 D5 A2
7 5 28
6
A6 D6
47K 8 4 30
7
A7 D7
47K
9 42 16
A8 D8
47K 10
41 18
A9 D9
47K 11 40 20
A10 D10
Note: PB1 is the sw pin:
47K 12 39 22
A11 D11
47K 13 38 25 PB1=0 means test sw runs
A12 D12
47K
14 37 27
PB1=1 means appl sw runs
A13 D13
47K
15 36 29
A14 D14
16 35 31
A15 D15_A1*
17 34
VCC
A16
18 3 2
A17 DU
32
C4005 13
0.1uF
Note:
The following symbol denotes the existence of a test point
0
19 on the PCB.
MODEL TCN6273N
0
19 N4
1
18 N4
2
2 N4
3
17 N4
4
6 N4
5
5 N4
VCC
3 4 5
32
C4004
VCC
0.1uF
24
EN_OE
29
EN_WE
22
U4002
CS1
30
CS2
12 13
0
A0 D0
11 14
1
A1 D1
10 15
2
A2 D2
9 17
3
A3 D3
8 18
4
A4 D4
7 19
5
A5 D5
6 20
6
A6 D6
5 21
7
A7 D7
27
A8
26
A9
23
A10
25
A11
4
A12
28
A13
3
A14
31
A15 0 1 2 3 4 5 6 7
2 1
A16 NC
VSS
16
C4007
VCC
0.1uF
16
IO_CS(0:4)
VCC 15 0
Y0
14
1
Y1
13
2
Y2
12 3
Y3
11 4
Y4
10 12
U4004
Y5
9 11
Y6 U4201 CS_LATCH*
7 13
Y7
GND
8
I/O chip select decoder
HOST CORE
68P81094E31-I
Schematics (Sheet 9 of 36)
7/28/2007