Motorola MTR2000 Manual page 107

STATION CONTROL MODULE
MODEL TCN6273N
68P81094E31-I
Schematics (Sheet 8 of 36)
7/28/2007
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SERVICE NOTES HOST CORE
Signal
Description/Nominal Signal Levels
Path
VCC pin connected to the Battery Backup pin of U4007, to preserve the RAM content in case of power failure.
A
Host Data Bus is split in 2 by the U4005 buffer: Host_Master_Data
B
bus connects the memory devices and Host_Data bus connects the rest of the IC's (I/O's) on this data bus.
While in Read mode, R4050 is not placed and the RP pin on the flash IC (U4003) is tied to the Reset pin on the
C
processor via D4002, and the boot block is locked. When the Boot Block needs to be programmed (Write
mode), R4050 is soldered in and the RP pin is tied to 12V via D4003 and R4050.
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SCHEMATIC IC'S TABLE HOST CORE
Reference Type Description
U4000 MC68356 Signal Processing Communication Engine
U4001,2 HM628128 CMOS Static RAM, 128 * 8 byte
U4003 AT49F8011 1 Meg *16 Boot Block Flash Memory
U4004 MC74AC138 1 of 8 Decoder/Demultiplexer
U4005 MC74AC245 Octal Bidirectional Transceiver With 3-State I/O
U4006...
MC74AC08 Quad 2 input AND Gate
U4007 MAX703 µP Supervisory Circuit with Battery Backup
U4201... MC74AC32 Quad 2-input OR gate