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Chapter 3
Configure SDRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to SPD enables
SDRAMFrequency, SDRAM CAS Latency and SDRAM Bank Interleave
automatically to be determined by BIOS based on the configurations on
the SPD. Selecting User allows users to configure these fields manually.
SDRAM Frequency
Use this item to configure the clock frequency of the installed SDRAM.
Settings options: 266MHz, 333MHz, Auto.
SDRAM CAS# Latency
This controls the timing delay (in clock cycles) before SDRAM starts a
read command after receiving it. Settings: Auto, 1.5, 2, 2.5, 3.0 (clocks).
2 (clocks) increases the system performance the most while 3 (clocks)
provides the most stable performance.
SDRAM Bank Interleave
This field selects 2-bank or 4-bank interleave for the installed SDRAM.
Disable the function if 16MB SDRAM is installed. Settings: Disabled, 2-
Way and 4-Way.
3-12
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