Gigabyte MZ32-AR1 User Manual page 106

Parameter
PCIe Root Port UnCorr Err
Mask Reg
PCIe Root Port UnCorr Err
Sev Reg
PCIe Device Corr Err Mask
Reg
PCIe Device UnCorr Err
Mask Reg
PCIe Device UnCorr Err Sev
Reg
CCIX GHES Deferred ERR
Notify Type
CCIX GHES Corrected Err
Notify Type
DDR4 DRAM Hard Post
Package Repair
HEST DMC Structure
Support
RAS EINJ Mode
BIOS Setup
Description
Initialize the PCIe AER Uncorrected Error Mask register of Root Port.
Initialize the PCIe AER Uncorrected Error Severity register of Root Port.
Initialize the PCIe AER Corrected Error Mask register of PCIe device.
Initialize the PCIe AER Uncorrected Error Mask register of PCIe device.
Initialize the PCIe AER Uncorrected Error Severity register of PCIe
device.
Selects the Notification type for CCIX deferred error.
Options available: Polled, SCI. Default setting is Polled.
Selects the Notification type for CCIX corrected error.
Options available: Polled, SCI. Default setting is Polled.
This feature allows spare DRAM rows to replace malfunctioning rows via
an in-field repair mechanism.
Options available: Enabled, Disabled. Default setting is Disabled.
HEST DMC (Deferred Machine Check) Structure Support.
Options available: Enabled, Disabled. Default setting is Disabled.
BIOS: Send APEI EINJ actions to PSP via CPM EINJ SMI callback;
PSP: Send APEI EINJ actions to RSP via PSP Mailbox.
Option available: BIOS, PSP. Default setting is PSP.
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