Sony SAT-W60 Service Manual page 40

8 7
+ 3 _ 3 V
CONFIG_BITS<25..0>\I
1 1 1
R1225 R1224 R1223
4.7K 4.7K 4.7K
D
5 % 5 % 5 %
6 0 3 6 0 3 6 0 3
2 2 2
3 3 3
+ 3 _ 3 V
UART S M C
C
S M A R T S M A R T 4640
1 1 1 1
R1222 R1221 R1220
4.7K 4.7K 4.7K
5 % 5 % 5 %
1/16W 6 0 3 6 0 3
2 2 2 2
TK
6 0 3
SERIAL SERIAL 5230
3 3 3 3
1 0
UART CONFIG CPU CONFIG
B
RIO_ADDR[23] - USE 1/2 CLOCK MULTIPLIERS FOR CPU
R1223
HI-USE 1/2 CLOCK MULTIPLIERS (2.5X/3.5X)
LO-USE INT CLOCK MULTIPLIERS (2X/3X)
RIO_ADDR[22] - SMART CARD #1 ENABLE.
R1222
HI-ENABLES SMART CARD PORT #1.
LO-DISABLES SMART CARD PORT #1.
RIO_ADDR[21] - SMART CARD #0 ENABLE.
R1221
HI-ENABLES SMART CARD PORT #0.
LO-DISABLES SMART CARD PORT #0.
RIO_ADDR[20] - CPU TYPE.
R1220
HI-WHEN USING AN IDT 4640 CPU.
LO-WHEN USING A QED 5230 CPU.
A
RIO_ADDR[19] - ENDIANESS.
R1219
HI-SYSTEM RUNS IN BIG ENDIAN MODE.
LO-SYSTEM RUNS IN LITTLE ENDIAN MODE.
RIO_ADDR[18] - SDRAM SPEED.
R1218
HI-CONNECTED BETWEEN 1 AND 2 (PULLED UP) = CAS LATENCY 2
LO-CONNECTED BETWEEN 2 AND 3 (PULLED DOWN) = CAS LATENCY 3
RIO_ADDR[17] - CPU PIPELINE CLOCK SPEED.
R1217
HI-PIPELINE CLOCK = 2X BUS CLOCK.
LO-PIPELINE CLOCK = 3X BUS CLOCK.
8 7
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6
1 1 1 1 1
R1219 R1218 R1217 R1216 R1215 R1214
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
5 % 5 % 5 % 5 % 5 % 5 %
6 0 3 6 0 3 6 0 3 6 0 3 6 0 3 6 0 3
2 2 2 2 2
3 3 3 3 3
RIO_ADDR[16:15] - CPU OUTPUT DRIVER SLEW RATE.
R1216, R1215
UP , UP OUTPUT DRIVERS AT 83%
UP , DOWN OUTPUT DRIVERS AT 100%
DOWN, UP OUTPUT DRIVERS AT 50%
DOWN, DOWN OUTPUT DRIVERS AT 67%
RIO_ADDR[4] - ENHANCED CPU INTERFACE ENABLED (USE WITH EXTERNAL BRIDGE CHIPS)
R1204
HI-ENHANCED MODE ENABLED
LO-ENHANCED MODE DISABLED
RIO_ADDR[3] - VIDEO MODE
R1203
HI-ENABLED PAL MODE
LO-ENABLES NTSC MODE
RIO_ADDR[2] - HARD DISK PRESENT
R1202
HI-NO HARD DISK
LO-HARD DISK PRESENT
RIO_ADDR[0] - ROMS ARE WORD/BYTE WIDTH
R1200
HI-ROMS ARE WORD (16 BIT) WIDTH
LO-ROMS ARE BYTE (8 BIT) WIDTH
TITLE=BLK_CFG
A B B R E V = B C F G
LAST_MODIFIED=Mon Jun 19 13:05:49 2000
6 5
5 4
1 1 1 1 1
R1213 R1212 R1211 R1210 R1209
4.7K 4.7K 4.7K 4.7K 4.7K
5 % 5 % 5 % 5 % 5 %
6 0 3 6 0 3 6 0 3 1/16W 1/16W
2 2 2 2 2
TK TK
6 0 3 6 0 3
3 3 3 3 3
BOARD TYPE
6
BOARD REV.
(LC3-SAT) 6
0 = LC2 (SOLO)
1 = LC3-DEV (SOLO) (DVT-2.3)
2 = 5230-J (SOLO)
3 = LC3-DEV2 (SOLO2)
4 = ...
5 = ...
6 = LC3-SAT
This document contains privileged or otherwise legally protected
information.
than the recipient is not authorized.
or otherwise use this document unless you are an authorized
representative of a named recipient.
DRAWING
SET:
ENGINEER:
4
3 2
1 1 1 1 1
R1208 R1207 R1206 R1205 R1204
4.7K 4.7K 4.7K 4.7K 4.7K
5 % 5 % 5 % 5 % 5 %
1/16W 6 0 3 6 0 3 1/16W 6 0 3
2 2 2 2 2
TK TK
6 0 3 6 0 3
3 3 3 3 3
C P U B U S M A S T E R
PRESENT
RESERVED
VIDEO INVERSION
R1205 - LOW IS INVERTED
R1205 - HIGH IS NORMAL
Software Bits:
<14..12> BOARD TYPE
<11..8> BOARD REVISION
<7..6> RESERVED
<3> 0 = NTSC; 1 = PAL
<2> 0 = DISK; 1 = FLASH
C WEBTV NETWORKS, INC. 1999
Disclosure of this information to anyone other
You may not read, copy,
E L M E R CONFIG
BLOCK: DATE:
SLEATOR/FULLER APPROVED:
3 2
1
1 1
R1201 R1200
4.7K 4.7K
5 % 5 %
D
6 0 3 6 0 3
2 2
3 3
C
1 1
R1203 R1202
4.7K 4.7K
5 % 5 %
6 0 3 6 0 3
2 2
3 3
B
A
REVISION: 0.0
B L O C K
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