Sony SAT-W60 Service Manual page 20

8 7
CPU_CLK\I
CPU_CRESET_N\I CPU_CRESET_N\I
CPU_SRESET_N\I CPU_SRESET_N\I
D
+ 3 _ 3 V
C
1 R0301
R0311
4.7K
4.7K 5 %
5 %
6 0 3
6 0 3
2
3
POWER_OK\I
CPU_WRRDY_N\I
CPU_EXTRQST_N\I
CPU_VALIDIN_N\I
CPU_MODEIN\I
B
CPU_INT_N\I
FUD_INT_N\I
DIAG_INT_N\I
CPU_VCCOK\I
INT<5> IS RESERVED
FOR TIMER
+ 3 _ 3 V
R 0 3 0 2
4.7 5 %
6 0 3
C 0 3 0 5 C 0 3 0 6 C 0 3 0 7
0.1UF 10UF 1.5NF
2 0 % 2 0 % 2 0 %
50V 10V 50V
C E R M C E R M C E R M
8 0 5 1210 8 0 5
R 0 3 0 3
A
4.7 5 %
6 0 3 + 3 _ 3 V
8 7
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6 5
CPU_CLK\I 41
M A S T E R C L O C K
68
COLDRESET_N
67
RESET_N
R M 5 2 3 1
70
BIGENDIAN
R0312
R0310
4.7K
4.7K
5 %
5 %
6 0 3
6 0 3
34 R D R D Y _ N
35 W R R D Y _ N
66 EXTRQST_N
36 VALIDIN_N
33 MODEIN
65 NMI_N
59 INT_N<0>
60 INT_N<1>
61
INT_N<2>
62
INT_N<3>
63
INT_N<4>
INTERRUPTS
64
INT_N<5>
69
V C C O K
C P U _ V C C P
39 V C C P
C P U _ V S S P
40 VSSP
+ 2 _ 5 V
DRAWING
TITLE=BLK_CPU
A B B R E V = B C P U
LAST_MODIFIED=Tue Mar 21 17:56:15 2000
6 5
4 3
U0301
S Y S _ A D < 3 1 >
S Y S _ A D < 3 0 >
S Y S _ A D < 2 9 >
S Y S _ A D < 2 8 >
S Y S _ A D < 2 7 >
S Y S _ A D < 2 6 >
S Y S _ A D < 2 5 >
S Y S _ A D < 2 4 >
S Y S _ A D < 2 3 >
S Y S _ A D < 2 2 >
S Y S _ A D < 2 1 >
S Y S _ A D < 2 0 >
S Y S _ A D < 1 9 >
S Y S _ A D < 1 8 >
S Y S _ A D < 1 7 >
S Y S _ A D < 1 6 >
S Y S _ A D < 1 5 >
S Y S _ A D < 1 4 >
S Y S _ A D < 1 3 >
S Y S _ A D < 1 2 >
S Y S _ A D < 1 1 >
S Y S _ A D < 1 0 >
S Y S _ A D < 9 >
S Y S _ A D < 8 >
S Y S _ A D < 7 >
S Y S _ A D < 6 >
S Y S _ A D < 5 >
S Y S _ A D < 4 >
S Y S _ A D < 3 >
S Y S _ A D < 2 >
S Y S _ A D < 1 >
S Y S _ A D < 0 >
S Y S _ A D C < 3 >
S Y S _ A D C < 2 >
S Y S _ A D C < 1 >
S Y S _ A D C < 0 >
S Y S _ C M D < 8 >
S Y S _ C M D < 7 >
S Y S _ C M D < 6 >
S Y S _ C M D < 5 >
S Y S _ C M D < 4 >
S Y S _ C M D < 3 >
S Y S _ C M D < 2 >
S Y S _ C M D < 1 >
S Y S _ C M D < 0 >
S Y S _ C M D P
BUS INTERFACE RELEASE_N
VALIDOUT_N
M O D E C L O C K
JTDO
JTDI
JTCK
JTAG
JTMS
NC_PIN<11>
NC_PIN<10>
N C _ P I N < 9 >
N C _ P I N < 8 >
P O W E R & G R O U N D N C _ P I N < 7 >
N C _ P I N < 6 >
N C _ P I N < 5 >
N C _ P I N < 4 >
N C _ P I N < 3 >
N C _ P I N < 2 >
NC_PIN<1>
N C _ P I N < 0 >
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E L M E R
SET:
ENGINEER:
4
2
108 31 CPU_AD<31..0>\I CPU_AD<31..0>\I
107 3 0
104 2 9
103 2 8
92 2 7
91 2 6
88 2 5
87 2 4
86 2 3
85 2 2
82 21
81 2 0
19
78
18
77
17
76
16
73
24 15
21 14
20 13
19 12
16 11
15 10
12 9
11 8 + 3 _ 3 V
10 7
9 6
6 5
5 4
122 3
R 0 3 0 4 R 0 3 0 5 R 0 3 0 6 R 0 3 0 7
121 2
118 1
4.7K 4.7K 4.7K 4.7K
117 0
5 % 5 % 5 % 5 %
6 0 3 6 0 3 6 0 3 6 0 3
112 S Y S _ A D C < 3 >
109 S Y S _ A D C < 2 >
116 S Y S _ A D C < 1 >
115 S Y S _ A D C < 0 >
55 8
54 7
6
53
C P U _ C M D < 4 > \ I
5
51
C P U _ C M D < 2 > \ I
4
50
C P U _ C M D < 8 > \ I
3
47
2
46
1
45
0 CPU_CMD<8..0>\I
44
56
38 + 3 _ 3 V + 3 _ 3 V + 3 _ 3 V + 3 _ 3 V + 3 _ 3 V
37
27
R 0 3 0 8 R0313 R0314 R0315 R0316
10K
28 5 % 4.7K 4.7K 4.7K 4.7K
1/16W 5 % 5 % 5 % 5 %
29 TK 6 0 3 6 0 3 6 0 3 6 0 3
6 0 3
30
C P U _ C M D < 0 > \ I
31 CPU_CMD<1>\I
C P U _ C M D < 3 > \ I
128 C P U _ C M D < 5 > \ I
127 C P U _ C M D < 6 > \ I
126 C P U _ C M D < 7 > \ I
125
100
99
98
97
96
95
2
1
CPU_RELEASE_N\I
Q F P
CPU_VALIDOUT_N\I
CPU_MODECLK\I
C WEBTV NETWORKS, INC. 1999
Disclosure of this information to anyone other
You may not read, copy, B L O C K
C P U
BLOCK: DATE:
SET
SLEATOR/FULLER APPROVED:
3 2
1
D
R0317 R0318 R0319 C
4.7K 4.7K 4.7K
5 % 5 % 5 %
6 0 3 6 0 3 6 0 3
+ 3 _ 3 V + 3 _ 3 V
B
R 0 3 2 0 R0321
4.7K 4.7K
5 % 5 %
6 0 3 6 0 3
A
REVISION: 0.0
PAGE: 1 of 2
REVISION:
PVT
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