Lexmark X940E Technical Reference page 309

Standard Protocol Data Transfer Sequence
The following illustration shows the typical data transfer sequence on the parallel
interface. See Table 8-1 for typical parallel interface timings on the parallel interface.
•
Uses standard transistor-transistor logic (TTL) levels for all interface control
signals and input data. Interface conditions are based on TTL levels. All
printer outputs are totem-pole TTL devices. All printer input/output (I/O) are
devices with an internal pull-up resistor to 5 V. Rise and fall times of each
signal must be less than 1,500 nanoseconds (ns) without slope reversal.
DATA1-8
STROBE*
BUSY
ACK*
8-7
A B C
D
Interfaces
G
F
E