Dsp96002 Port A/B User Sram Decoder/Partitions; Table 2-5 Port A/B User Eprom Selection - Motorola DSP96002ADM User Manual

Table of Contents

Advertisement

EPROM TYPE
2 K × 8
4 K × 8
8 K × 8
16 K × 8
32 K × 8
64 K × 8
2.4.4

DSP96002 Port A/B User SRAM Decoder/Partitions

The DSP96001ADM includes sixteen 64 K
(MCM6209) that provide a working area for user programs and data with zero wait state
access.
Note:
The SRAM sockets will also accept sixteen 256 K
which can be used to replace the 64 K
required.
Port A and Port B both have 64 K
The SRAMs may be moved to various blocks of memory and may be partitioned so that
P, X and/or Y memory spaces have external memory. Since only the upper 8 bits of the
address bus are input into the PAL, either the 64 K
the DSP96002ADM. The SRAM decoder does not have bus arbitration signals as
qualifiers; therefore, any processor that becomes the bus master may directly access the
SRAMs. This is useful in shared memory configurations. The SRAM address lines are
buffered to decrease the DSP96002 address bus loading.
There are two jumpers (JG17, JG18) for Port A and two jumpers (JG23, JG25) for Port B.
Jumpers JG17 (Port A) and JG25 (Port B) are for memory block selection while jumpers
JG18 (Port A) and JG23 (Port B) are for memory map partitioning of the SRAM for the
three DSP96002 memory spaces. The following tables show the jumper options that will
provide one of five address block selections and a few of the different memory map
partitions possible for the SRAM. There are a variety of memory map partitions due to
the minimal address decoding done in the PAL and the number of combinations
achievable by programming the DSP96002 Port Select Register (PSR).
MOTOROLA

Table 2-5 Port A/B User EPROM Selection

JG7–10 / JG11–14
1–2
1–2
1–2
2–3
2–3
2–3
×
32 words of SRAM for user program development.
DSP96002ADMUM/AD, Preliminary
DSP96002ADM Technical Summary
Configuring the DSP96002ADM
JG15/JG16
11–12, 17–18, 19–20
11–12, 15–16, 19–20
9–10, 13–14, 21–22
9–10, 13–14, 21–22
9–10, 13–14, 21–22
9–10, 13–14, 21–22
×
4-bit high speed CMOS Static RAMs
×
4-bit SRAM (MCM6228),
×
4-bit SRAM chips if more memory is
×
4 or 256 K
×
4 device will work with
2-11

Advertisement

Table of Contents
loading

Table of Contents