Alinco DJ-175 Service Manual page 5

3) PLL Synthesizer System
1. PLL
The dividing ratio is obtained by sending data from the CPU (IC113) to pin 10
and sending clock pulse to pin 9 of the PLL IC ( IC101 ). The oscillated signal
from the VCO is amplified by the buffer (Q116) and input to pin 8 of IC102.
Each programmable divider in IC102 divides the frequency of the input signal
by N according to the frequency data, to generate a comparison frequency of
5 or 6.25kHz.
2. Reference Frequency Circuit
The reference frequency appropriate for the channel steps is obtained by
dividing the 21.25MHz reference oscillation (X102) by 4250 or 3400,
according to the data from the CPU (IC113). When the resulting frequency is
5kHz, channel steps of 5, 10, 15, 20, and 30kHz are used. When it is 6.25kHz,
channel steps of 12.5, 25 , and 50kHz are used.
3. Phase Comparator Circuit
The PLL (IC102) uses the reference frequency, 5 or 6.25kHz. The phase
comparator in the IC102 compares the phase of the frequency from the VCO
with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the
internal divider in IC102.
4. PLL Loop Filter Circuit
If a phase difference is found in the phase comparison between the reference
frequency and VCO output frequency, the charge pump output (pin 5) of IC102
generates a pulse signal, which is converted to DC voltage by the PLL loop
filter and input to the varicap of the VCO unit for oscillation frequency control.
5. VCO Circuit
A Colpitts oscillation circuit driven by Q108 directly oscillates the desires
frequency. The frequency control voltage determined in the CPU (IC113) and
PLL circuit is input to the varicaps (D105 and D107). This change the
oscillation frequency, which is amplified by the VCO buffer (Q113) and output
from the VCO unit.