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MAIN(GA) SCHEMATIC DIAGRAM
0
1
MAIN(GA)
TO OP DRV
VDIRS
HDIRS
TO MAIN IF(CN105),
P.PRCS
TG_VD
TG_HD
MCLKI
TO SUB CPU,P.PRCS
AFE_RST
REG_3.1V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
36
35
34
TG_VD
TG_HD
C4402
0.1
MCLKI
37 TRST
38 NC
39 NC
40 NC
R4413
1k
TG_VD
41 VDTG
42 NC
43 NC
R4414
1k
TG_HD
44 HDTG
45 NC
46 NC
47 NC
MCLKI
48 MCLKI
1
2
3
L4401
NQR0129-002X
C4401
4.7
(No.YF139)2-19
LAST NO.
IC
L
R
C
33
32
31
30
29
28
27
26
25
SDT
24
NC
23
SEN
22
NC
21
SCK
20
IC4401
NC
19
JCY0228
NC
18
VDCCD
17
NC
16
NC
15
NC
14
HDCCD
13
4
5
6
7
8
9
10
11
12
2-20(No.YF139)
VACANT NO.
4401
4401
4414
4404,4407,4408,4409
4403
GA_SI
GA_SEN
GA_SCK
VDCCD
HDCCD
SSGFLD
GA_SI
GA_SEN
GA_SCK
R4406
1k
VDCCD
R4405
1k
HDCCD
SSGFLD
FLDCPU
VDCPU
yf139_y30346001a_rev1.2
TO P.PRCS,OP DRV
CAM_VD
TO P.PRCS
GA_SI
GA_SEN
GA_SCK
VDCCD
HDCCD
SSGFLD
TO DSP,P.PRCS
TO DSP,P.PRCS
FLDCPU
VDCPU
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