Reset Circuit (Watch Dog Timer); Sram And Rtc Backup Circuit - Panasonic KX-FM89BX Service Manual

6.3.7. RESET CIRCUIT (WATCH DOG TIMER)

The output signal from pin 1 of the voltage detect IC (IC507) is input to the ASIC (IC501) 136 pin.
Then the output signal from pin 133 of the ASIC (IC501) resets the ASIC.
1. During a momentary power interruption, a positive reset pulse of
46~51 msec is generated and the system is reset completely.
2. When pin 132 and 133 of IC501 become low level, they will
prohibit the SRAM (IC503) from changing data.
The SRAM (IC504) will go into the backup mode, when they are
backed up by a lithium battery.
3. The watch dog timer, built-in the ASIC (IC501), is initialized by the
CPU about every 1.5 ms.
When a watch dog error occurs, pin 137 of the ASIC (IC501)
becomes low level.
The terminal of the WDERR signal is connected to the reset line,
so the WDERR signal works as the reset signal.

6.3.8. SRAM AND RTC BACKUP CIRCUIT

1. Function
This unit has a lithium battery (BAT501) which works for the
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