Functional Block Diagram; Device Information - Marantz NR1200 Service Manual

FUNCTIONAL BLOCK DIAGRAM

4. Block Diagram and Functions
LDOE TVDD VDD18
LDO
BICK/DCLK
LRCK/DSDL1 Soft Mute
SDTI1/DSDR1 PCM
Data
SDTI2/DSDL2 Interface
De-empha
SDTI3/DSDR2/TDMO1
sis
DSD Filter
SDTI4/DSDL3/TDMO2
Soft Mute
DSD
Data
Interface
DSD Filter
DSDR3
DSDL4
DSDR4
Soft Mute
DSD Filter
DZF/SMUTE
CAD1/DCHAIN
Soft Mute
DSD Filter
I2C
CAD0_I2C/CSN/DIF
Control
Register
SCL/CCLK/TDM1
SDA/CDTI/TDM0
PS/CAD0_SPI
Figure 1. Block Diagram
014011794-E-00
[AK4458]
DVSS PDN AVDD AVSS
Bias
DATT AOUTL1P
8X SCF
Interpolator
AOUTL1N
VREFH1
Vref
DATT Modulator
VREFL1
Soft Mute
Noise
Rejection
Filter
AOUTR1P
SCF
AOUTR1N
DATT AOUTL2P
8X SCF
Interpolator
AOUTL2N
VREFH2
Vref
DATT Modulator VREFL2
Soft Mute
Noise
Rejection
Filter
AOUTR2P
SCF
AOUTR2N
DATT AOUTL3P
8X SCF
Interpolator
AOUTL3N
VREFH3
Vref
DATT
Modulator
VREFL3
Soft Mute
Noise
Rejection
Filter
AOUTR3P
SCF
AOUTR3N
DATT 8X
AOUTL4P
SCF
Interpolator
AOUTL4N
VREFH4
Vref
DATT Modulator VREFL4
Soft Mute
Noise
Rejection
Filter
AOUTR4P
SCF
AOUTR4N
Clock
Divider
MCLK
2015/01
- 5 -
SLAS764 – MAY 2011
PCM5100A (DIGITAL : U1052, U1053) TERMINAL FUNCTIONS, PCM510x
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
I/O DESCRIPTION
NAME NO.
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
DEMP 10 I De-emphasis control for 44.1kHz sampling rate
FLT 11 I Filter select : Normal latency (Low) / Low latency (High)
SCK 12 I System clock input
BCK 13 I Audio data bit clock input
DIN 14 I Audio data input
PCM5100, PCM5101, PCM5102
LRCK 15 I Audio data word clock input
FMT 16 I Audio format selection : I
SLAS764 – MAY 2011
XSMT 17 I Soft mute control : Soft mute (Low) / soft un-mute (High)
Table 1. Differences Between PCM510x Devices
LDOO 18 - Internal logic supply rail terminal for decoupling
Part Number
DGND PCM5102 19 - Digital ground
PCM5101
DVDD 20 - Digital power supply, 3.3V
PCM5100
spacer (1) Failsafe LVCMOS Schmitt trigger input
PCM5100 Block Diagram
DIN (i2s)
Zero
Data
Detector
Clock Halt
Detection
LRCK
BCK
PLL Clock
6
MCK UVP/Reset
Figure 1. PCM510x Functional Block Diagram
50

DEVICE INFORMATION

PCM510X (top view)
(1)
: Off (Low) / On (High)
2 S (Low) / Left justified (High)
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Dynamic Range SNR THD
112dB 112dB –93dB
106dB 106dB –92dB
100dB 100dB –90dB
Current LINE OUT
Segment
DAC
Current
Segment
DAC
Advanced Mute Control
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
Power
Supply DVDD (3.3V)
Copyright © 2011, Texas Instruments Incorporated
POR Ch. Pump
GND
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