Pin Description - Marantz NR1200 Service Manual

W9864G6KH-6(DIGITAL : U1020)

Pin description

5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
23 ~ 26, 22,
A0 A11 Address
29 ~35
20, 21 BS0, BS1 Bank Select
2, 4, 5, 7, 8, 10,
Data
11, 13, 42, 44,
DQ0 DQ15
45, 47, 48, 50,
Input/ Output
51, 53
19 Chip Select
CS
Row Address
18
Strobe
Column
17
CAS Address Strobe Referred to
16 Write Enable
WE
UDQM
Input/output
39, 15
mask
LDQM
38 CLK Clock Inputs
37 CKE Clock Enable
1, 14, 27 V Power
DD
28, 41, 54 V Ground
SS
Power for I/O
3, 9, 43, 49 V
DDQ
buffer
Ground for I/O
6, 12, 46, 52 V
SSQ
buffer
36, 40 NC No Connection No connection.
W9864G6KH
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A11. Column address: A0 A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock , CAS and WE define the
operation to be executed.
Referred to
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from V , to improve DQ noise
DD
immunity.
Separated ground from V , to improve DQ noise
SS
immunity.
Publication Release Date: Nov. 12, 2013
- 5 - Revision A02
Block diagram
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENER ATOR
RAS
COMMAND
CAS
DECODER
WE
A10
MODE
A0
REGIST ER
ADDRESS
A9
A11 BUFFER
BS0
BS1
COLUMN
REFRESH
COUNTER
COUNTER
NOTE:
T he cell array configuration is 4096 * 256 * 16
48
COLUMN DECODER
COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #0 BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
DATA CONTROL DQ
CIRCUIT BUFFER
COLUMN DECODER COLUMN DECODER
CELL ARRAY CELL ARRAY
BANK #2 BANK #3
SENSE AMPLIFIER SENSE AMPLIFIER
Publication Release Date: Nov. 12, 2013
- 6 - Revision A02