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MAIN(JACK) SCHEMATIC DIAGRAM
MAIN(JACK)
0
1
DV JACK
J102
QNZ0822-001
DC JACK
J101
QNA0040-001
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-29(No.YF124)
D102
3
4
2
5
1
C101
TO PARAGON
GND
TPA+
TPA-
TPB+
TPB-
GND
BATT_+
ADP_DC
ADP_L
GND
yf124_y40164001a_rev0.1
TO MAIN IF
(CN101),REG
TO REG
TO CPU
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