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Busy Flag (BF)
When the busy flag is set at a logical "1", the LCD
unit is executing an internal operation, and no in-
struction will be accepted. The state of the busy flag
is output on data line DB
selection signals RS = 0, R/W = 1 as shown in Table
3. The next instruction may be entered after the
busy flag is reset to logical "0".
Address Counter (AC)
The address counter generates the address for
the display data RAM and character generator
RAM. When the address set instruction is written
into the instruction register, the address information
is sent to the address counter. The same instruciton
also determines which of the two RAM's is to be
selected.
After data has been written to or read from the
display data RAM or character generator RAM, the
address counter is automatically incremented or
decremented by one. The contents of the address
counter are output on data lines DB
response to the register selection signals RS = 0,
R/W = 1 as shown in Table 3.
Display Data RAM (DD RAM)
This 80 x 8 bit RAM stores up to 80 8-bit character
codes as display data. The unused area of the RAM
may be used by the microprocessor as a general
purpose RAM area.
The display data RAM address, set in the address
counter, is expressed in hexadecimal (HEX) num-
bers as follows:
High-order
Bits
AC
AC6 AC5 AC4 AC3 AC2 AC1 AC0
HEX
Digit
Example: DD RAM address '4E'
1
0
0
4
The address of the display data RAM corre-
sponds to the display position on the LCD panel as
follows:
Display Unit User's Manual
in response to the register
7
- DB
0
6
Lower-order
Bits
HEX
Digit
1
1
1
0
E
a. Address type a . . . .For dual-line display
Digit
1
2
3
Line 1
00
01
02
H
H
H
Line 2
40
41
42
H
H
H
When a display shift takes place, the addresses
shift is as follows:
01
02
03
Left
H
H
H
Shift
41
42
43
H
H
H
27
00
01
Right
H
H
H
Shift
67
40
41
H
H
H
The addresses for the second line are not con-
tinuous to the addresses for the first line. A 40-char-
acter RAM area is assigned to each of the two line
as follows:
line 1: 00
- 27
H
line 2: 40
- 67
H
in
For an LCD unit with a display capacity of less
than 40 characters per line, characters equal in
number to the display capacity, as counted from
display position 1, are displayed.
b. Address type b . . . .For single-line display with
logically dual-line addressing
Digit
1
2
3
4
5
Line
00
01
02
03
04
H
H
H
H
1
When a display shift takes place, the addresses
shift as follows:
Left
01
02
03
04
05
H
H
H
H
Shift
Right
27
00
01
02
03
H
H
H
H
Shift
The right-hand eight characters, for the purposes
of addressing and shifting, may be considered to
constitute a second display line. For the address
type of each model, see Table 12.
Dot-Matrix LCD Units
Display Position
4
5
6
7
8
9
. . .
03
04
05
06
07
08
H
H
H
H
H
H
. . .
43
44
45
46
47
48
H
H
H
H
H
H
DD RAM Address (HEX)
. . .
04
05
06
07
08
09
H
H
H
H
H
H
. . .
44
45
46
47
48
49
H
H
H
H
H
H
. . .
02
3
04
05
06
07
0
H
H
H
H
H
H
. . .
42
43
44
45
46
47
H
H
H
H
H
H
H
H
Display Position
6
7
8
9
10
11
12
13
05
06
07
40
41
42
43
44
H
H
H
H
H
H
H
H
H
DD RAM Address (HEX)
06
07
08
41
42
43
44
45
H
H
H
H
H
H
H
H
04
05
06
67
40
41
42
43
H
H
H
H
H
H
H
H
39 40
26
27
H
H
66
67
H
H
27
00
H
H
67
40
H
H
25
26
H
H
65
66
H
H
14
15
16
45
46
47
H
H
H
46
47
48
H
H
H
H
44
45
46
H
H
H
H
5
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