Pin Configurations - Denon PMA-1600NE Service Manual

MX25L4006EM1I-12G (DIGITAL : U0705)

PIN CONFIGURATIONS

8-PIN SOP (150/200mil) 8-PIN PDIP (300mil)
1
CS# 8
CS# 1 VCC
8
2
SO/SIO1 7
SO/SIO1 2 7 HOLD#
WP# 3 6 SCLK
WP# 3 6
GND 4 SI/SIO0
5
GND 4 5
8-LAND, WSON (6x5mm) 8-LAND USON (2x3mm)
CS# 1 8 VCC CS# 1
SO/SIO1 2 HOLD# SO/SIO1 2
7
WP# 3 6 SCLK WP# 3
GND 4 SI/SIO0 GND 4
5
PCM1795 (INPUT : U0410)
Terminal Function
NAME NO. I/O
AGND1 19
AGND2 24 — Analog ground (internal bias)
AGND3L 27 — Analog ground (left channel DACFF)
AGND3R 16 — Analog ground (right channel DACFF)
BCK 6 I Bit clock input (1)
DATA 5 I Serial audio data input (2)
DGND 8 — Digital ground
IOUTL+ 25 O Left channel analog current output+
IOUTL– 26 O Left channel analog current output–
IOUTR+ 17 O Right channel analog current output+
IOUTR– 18 O Right channel analog current output–
IREF 20 — Output current reference bias pin
LRCK 4 I Left and right clock (fS) input (2)
MC 12 I Mode control clock input(2)
MDI 11 I Mode control data input (2)
MDO 13 I/O Mode control readback data output (3)
MS 10 I/OI Mode control chip-select input (4); active low
MSEL 3 I I2C/SPI select (2); active low SPI select
RST 14 I Reset (2); active low
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
VCC
Serial Data Input (for 1 x I/O) / Serial Data
HOLD# SI/SIO0
Input & Output (for Dual Output mode)
SCLK
Serial Data Output (for 1 x I/O) / Serial
SI/SIO0
SO/SIO1
Data Output (for Dual Output mode)
SCLK Clock Input
WP# Write Protection
8 VCC
Hold, to pause the device without
HOLD#
HOLD#
7
deselecting the device
6 SCLK
VCC + 3.3V Power Supply
SI/SIO0
5
GND Ground
DESCRIPTION
NAME NO. I/O
SCK 7 I
VCC1 23 —
VCC2L 28 —
VCC2R 15 —
VCOML 22 —
VCOMR 21 —
VDD 9 —
ZEROL 1 I/O
ZEROR 2 I/O
(1) Schmitt-trigger input, 5-V tolerant.
(2) Schmitt-trigger input, 5-V tolerant.
(3) Schmitt-trigger input and output. 5-V tolerant input. In I2C mode, this pin becomes an open-drain
3-state output; otherwise, this pin is a CMOS output.
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
31
DESCRIPTION
System clock input(2)
Analog power supply, 5 V
Analog power supply (left channel DACFF), 5 V
Analog power supply (right channel DACFF), 5 V
Left channel internal bias decoupling pin
Right channel internal bias decoupling pin
Digital power supply, 3.3 V
Zero flag for left channel (4)
Zero flag for right channel (4)