Kenwood TM-321A Service Manual page 9

-321A
CIRCUIT DESCRIPTION
@
Reset backup circuit
Fig.
10
shows the
reset
backup circuit. When the
transceiver
is
turned
ON,
3.0V
is
applied at the
INT4
pin causing
!C3 to enter the backup mode.
(C2
timing chart
Pin
1
Pin
3
Fig.
10 Reset and backup circuit
10
@
PLL
data
output
PLL
data
is
supplied from pins P92
(CK},
P91
(DT),
and P90
(RST) of the
microprocessor.
Fig.
11
shows
the data transfer format.
Fig.
12 shows the data con-
figuration.
21bit
OT
MSB LSB
RS
Fig.
11
PLL
data transfer format
LSB
MsB
1
2 3 4
51617
ratio
A
Main
counter
frequency division
ratio
N
Port setting,
comparison frequency
selection
Shift
register
SC
D3
D2
OUT
RESET
R16
32
CK
ot
90
2
44
7
IN
INT4
7
10
11
12 13 14 15 16 17 18 19 20
21
Pulse
swallow counter
frequency division
a
21
21 25
a
21
2
21 21
2
01
02
D3
The 21-bit
data
is
converted by the procedure below,
4.25V-
1.
Frequency division ratio data
A,
N
(17 bits)
F
(RX
display
-
30.825MHz)
=
[(N
X
128) + A]
X12.8MH2/ref
N
:
Frequency division ratio of
main
10-bit counter
A:
Frequency division ratio of 7-bit
pulse
swallow counter
td td
2. Comparison frequency (ref) selection (2 bits)
Data
Phase
comparison frequency
01 D2
L
L 5kHz 5, 10, 15, 20
or
25kHz
steps
3.
Switch
selection
(2
bits)
Data Output port
D3 D4
SW1
sw2
H
RX
mode
H
L
L
L
H
L
H
TX
mode
Fig.
12
PLL
data configuration
-321A
CIRCUIT DESCRIPTION
@
Reset backup circuit
Fig.
10
shows the
reset
backup circuit. When the
transceiver
is
turned
ON,
3.0V
is
applied at the
INT4
pin causing
!C3 to enter the backup mode.
(C2
timing chart
Pin
1
Pin
3
Fig.
10 Reset and backup circuit
10
@
PLL
data
output
PLL
data
is
supplied from pins P92
(CK},
P91
(DT),
and P90
(RST) of the
microprocessor.
Fig.
11
shows
the data transfer format.
Fig.
12 shows the data con-
figuration.
21bit
OT
MSB LSB
RS
Fig.
11
PLL
data transfer format
LSB
MsB
1
2 3 4
51617
ratio
A
Main
counter
frequency division
ratio
N
Port setting,
comparison frequency
selection
Shift
register
SC
D3
D2
OUT
RESET
R16
32
CK
ot
90
2
44
7
IN
INT4
7
10
11
12 13 14 15 16 17 18 19 20
21
Pulse
swallow counter
frequency division
a
21
21 25
a
21
2
21 21
2
01
02
D3
The 21-bit
data
is
converted by the procedure below,
4.25V-
1.
Frequency division ratio data
A,
N
(17 bits)
F
(RX
display
-
30.825MHz)
=
[(N
X
128) + A]
X12.8MH2/ref
N
:
Frequency division ratio of
main
10-bit counter
A:
Frequency division ratio of 7-bit
pulse
swallow counter
td td
2. Comparison frequency (ref) selection (2 bits)
Data
Phase
comparison frequency
01 D2
L
L 5kHz 5, 10, 15, 20
or
25kHz
steps
3.
Switch
selection
(2
bits)
Data Output port
D3 D4
SW1
sw2
H
RX
mode
H
L
L
L
H
L
H
TX
mode
Fig.
12
PLL
data configuration