Kenwood TM-321A Service Manual page 6

CIRCUIT DESCRIPTION
At
220MHz,
fVCO
(RX)
has
the
following
relationship to
the various frequency division ratios
:
f¥CO=(220-30.825)=[(n X
128) + AJ
X
fosc/R
where,
fVCO
:
Frequency output by the
VCO
n:
10-bit binary programmable counter setting
A:
7-bit binary
programmable counter setting
fosc
:
12.8MHz
reference oscillator
R
:
14-bit binary programmable counter setting
(2560)
If
n
=
295 and
A=
75, then;
fV¥CO=
[(295
X 128) + 75]
X
12800/2560
=(37760
+75]
X5
=189175kHz=189.175MHz
DRIVE(X59-3120-11)
1
8V
when
PLL
is
locked
TM-32
@
Unlock detector circuit
Whenever the
PLL
is
unlocked, pin 10
of the
PLL
IC goes
high
("H')
(5.5V),
turning
off
Q15
so
that
Q1 and
Q2
in
the module unit (drive unit) turn
OFF.
The
result
is
that during receive Q17
is
OFF,
and
during transmit
Q4
and Q5
in
the module unit
are
OFF.
This
halts trans-
mit, preventing unwanted radiation from the antenna.
(See
Fig. 6.)
PLL LOCKED Sw
in
transmit mode
OV when
PLL
is
unlocked
01
in
transmit mode
Qi
W
2!
RS
R7 R17
on
a
cog
LTT
Q2
|
Q4
R3 Re
C10
cs
Q5
8T
Sw
©
QUT
wo
sw
11
j
10
ae
4
3 2
1
a
FROM
PLL
OUT
TO
DRIVE TR
O19.
8V
when
PLL
locked in receive mode
eR
OV when
PLL
unlocked
in receive mode
c79
1c2
1.4V
when
PLL
is
locked
2
OV when
PLL
is
unlocked
M54959P
Q17
>
To
1st
RX
mixer
cso
5V
4
«
Og
% UNLOCK
C69
discharge is
delayed when
IN
8T
R89
5V
OV)
R71
D6
R62
Ov
5.5V)
Q15
sv
Low (OV)
when
PLL
is
locked
High
(5.5V)
when
PLL
is
unlocked
voltage
rises
and advanced when
voltage falls.
Fig.
6
PLL
unlock detector circuit
7