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1-3.
SCHEMATIC DIAGRAM – VMP Section (1/2) –
(1/2)
LA7
LA6
LA5
LA4
CN802
LA3
23P
LA2
D-OUT
LA1
D-GND
R921
100
V17
LA0
C2PO
R922
100
V16
GFS
R923
100
V15
FOK
(NC)
R925
0
V13
CD-DATA
R926
0
V12
CD-WCLK
R927
0
V11
CD-SCLK
(NC)
D-GND
R230
0
PWM3(RFDC)
R231
0
PWM2(TE)
R232
0
PWM1(FE)
R930
100
V8
XRST
DI
R931
100
V7
DATA
R946
R932
100
V6
1k
XLAT
CLK
R933
100
V5
CLK
R948
1k
R947
0
RFSW
R934
100
V4
SQSO
R935
100
V3
SENS
R936
100
V2
SQCK
R937
100
V1
SCOR
D/A CONVERTER
IC805
BH2220
FVM
R954
1.8k
R955
1.8k
R953
1.8k
CN803
9P
+7V
+7V
P-GND
P-GND
C501
47 10V
+3.3V
D-GND
D-GND
+3.3V(RF)
D-GND(RF)
D501
C502
UDZS3.3B
0.1
EP003
R502
Q501
(CHASSIS)
10k
2SC3266GR
B+ SWITCH
EP004
R501
(CHASSIS)
1k
FB804
R877
100
R858
100
LA14
R876
100
R859
100
LA13
R875
100
R860
100
LA8
R874
100
R861
100
LA9
R873
100
R862
100
LA11
R872
100
PROGRAM ROM
LOE
IC803
R871
100
R863
100
LA10
HT27C020
R870
100
R917
100
LCS3
R918
100
LD7
P3
P2
P1
R919
100
C923
0.01
R915
100
IC804
GLT44016-30TC
C848
0.1
D-RAM
C834
C835
C837
0.1
0.1
0.1
C830
0.1
C822
47
25V
C802
0.1
LA12
C801
FB806
47
LA13
25V
LA14
LA15
LA16
LA17
R804
AUDIOCLK
1k
AUDATA
BCLK
LR
AIN
ARCLK
ARFS
V11
R226
0
V13
R227
0
V12
R228
0
C862
100p
R913
100
R912
100
C836
FB805
47
25V
3
3
R802
R801
4.7k
4.7k
R837
100
V5
M1
V15
V16
VIDEO CD MPEG PROCESSOR
IC801
R945
ES3880FM
R944
R943
R942
R941
R940
R939
R938
R818
18
Q801
2SC3266
GR
R823
18
+3.3V REGULATOR
R833
C827
82
0.1
D804
1SS355
D801
UDZS
C806
3.9B
C805
C804
C803
47
0.1
0.1
0.1
R822
25V
100
CX-JV1
A2
AUX4
135MID
PCKCSCN
MPUCLK
HSYNC
VSYNC
100
YUV7
100
YUV6
100
YUV5
100
YUV4
100
YUV3
100
YUV2
A3
100
YUV1
A4
100
YUV0
A5
A6
(Page 4)
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
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