Sony CX-JV1 Service Manual page 56

CX-JV1
• VMP50 BOARD IC801 ES3880FM (VIDEO CD MPEG PROCESSOR)
Pin No. Pin Name
1 VDD3
2 RAS
3 DWE
4 to 12 MA0 to MA8
DBUS0 to
13 to 28
DBUAS15
29 RESET
30 GND
31 VDD3
32 to 39 YUV0 to YUV7
40 VSYNC
41 HSYNC
42 DCLK
43
PCLK2X
44
PCLK
45 AUX0
46 AUX1
47 CD ACK
48 AUX3
49 AUX4
50 GND
51 VDD3
52 AUX6
53 AUX5
54 AUX7
55 to 62 LD0 to LD7
63 LWR
64 LOE
65 LCS3
66 LCS1
67 LCS0
68 to 79 LA12 to LA17
80 GND
81 VDD5
82 to 87 LA0 to LA11
88 ACLK
AOUT/
89
SELPLL0
90
ATCLK
ATPS/
91
SELPLL1
92 DOE
93 AIN
94 ARCLK
95 ARFS
56
I/O
—
Power supply terminal (+3.3V)
O
Row address strobe signal output to the D-RAM
O Write enable signal output to the D-RAM
O
Address signal output to the D-RAM
I/O
Two-way data bus with the D-RAM
I
Reset signal input from the MPEG video/audio decoder "L": reset
—
Ground terminal
—
Power supply terminal (+3.3V)
O
YUV 8-bit video data bus output to the MPEG video/audio decoder
I
Vertical sync signal input from the MPEG video/audio decoder "L": active
I
Horizontal sync signal input from the MPEG video/audio decoder "L": active
I
System clock signal input from the MPEG video/audio decoder
I
27 MHz pixel clock signal input from the MPEG video/audio decoder
I
13.5 MHz pixel clock signal input from the MPEG video/audio decoder
I Guard frame sync signal input from the digital signal processor
I
Focus OK signal input from the digital signal processor
O Acknowledge signal input from the system controller
O
Serial data transfer clock signal output to the digital signal processor
O Interrupt request signal output to the MPEG video/audio decoder
—
Ground terminal
—
Power supply terminal (+3.3V)
O Strobe signal output to the system controller
O Strobe signal output to the MPEG video/audio decoder
O Serial data output to the system controller
I/O
Two-way data bus with the MPEG video/audio decoder Data input from the program ROM
O
Write enable signal output terminal Not used
O Output enable signal output to the program ROM
O
Chip enable signal output to the program ROM
O
Clock signal output to the MPEG video/audio decoder
O
Chip select signal output terminal Not used
O Address signal output to the program ROM
—
Ground terminal
—
Power supply terminal (+5V)
O
Address signal output to the program ROM
O Master clock signal output to the MPEG video/audio decoder
Audio data output to the MPEG video/audio decoder
O
Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at "L" in this set)
O
Audio bit clock signal (2.8224 MHz) output to the MPEG video/audio decoder
Audio frame sync signal output to the MPEG video/audio decoder
O Selection signal input terminal for the PLL clock frequency of the DCLK (IC802: pin qs) output
(fixed at "L" in this set)
O
Output enable signal output to the D-RAM
I Audio serial data input from the MPEG video/audio decoder
I
Audio bit clock signal (2.8224 MHz) input from the MPEG video/audio decoder
I
Audio frame sync signal input from the MPEG video/audio decoder
Description